VHDL parameterized constant

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campo85

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Hi all, I have a problem. I have coded a vhdl module with some generics to parameterized the design based on width bus. In the design I have a counter and I need to stop the counter when it has achieved the half value. So, I've declared a constant but Active HDL gives me an error. I declared the constant in this way :

Code: 
constant LENGTH_COUNTER : integer := integer(ceil(log2(real(WIDTH_MULTIPLIER))));	
constant STOP_COUNTER : std_logic_vector(LENGTH_COUNTER downto 0) := (LENGTH_COUNTER => '1', others => '0');
signal counter : std_logic_vector( LENGTH_COUNTER downto 0);

the error is :

# Error: COMP96_0597: modular_exponetiantiation.vhd : (42, 72): Aggregate with multiple choices has a non-static or null choice. Use -relax to compile aggregates composed of one non-static or null choice and choice others.
Click to expand...

I've also tried to declare in this way :

Code: 
constant LENGTH_COUNTER : integer := integer(ceil(log2(real(WIDTH_MULTIPLIER))));	
constant STOP_COUNTER : std_logic_vector(LENGTH_COUNTER downto 0) := (LENGTH_COUNTER => '1', LENGTH_COUNTER-1 downto 0 => '0');
signal counter : std_logic_vector( LENGTH_COUNTER downto 0);

But I get :


Can someone give me some tips ? Thanks for any reply.

Kind regards.
 

Seems to be a specific ActiveHDL problem. Try
Code: 
constant STOP_COUNTER : std_logic_vector(LENGTH_COUNTER downto 0) := std_logic_vector(to_unsigned(2**LENGTH_COUNTER,LENGTH_COUNTER+1));
 

As a side note - if all you are doing is checking for a half way value, instead of comparing the whole counter to a specified half value, why not just check the MSB? If the MSB is set, then it must be half way.
 

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