VHDL package body and

[shaiko]

As far as I know, a VHDL package is defined as follows :

What is the section in red for?

package some_package is
[COLOR="#FF0000"]-- but what is this region for...?[/COLOR]
end package some_package ;

package body some_package is
-- I know that this region contains function prototypes for example 
end package body some_package ;

 

[ads-ee]

It is for declarations.

 

[shaiko]

Can you describe a function in the package body without declaring it in the red section ?

 

[ads-ee]

I've always declared them. Don't know if you can avoid declaring it. You'll have to either look it up or wait till one of the VHDL experts responds.

 

[shaiko]

I see that it doesn't fail a parsing check...

 

[shaiko]

Information in this page suggests that a function declaration is optional...
**broken link removed**

VHDL experts...please leave your input.
In a package, is there anything that must be written only in the declaration section (and nowhere else)?
Can this part of a package be left blank with everything described in the package body?

 

[FvM]

Information in this page suggests that a function declaration is optional...
**broken link removed**.

The link doesn't talk about packages at all, just functions in general.

I see that it doesn't fail a parsing check...

Did you also try to import the function in your design? I presume the function without delarative part won't be visible.

 

[TrickyDicky]

Can you describe a function in the package body without declaring it in the red section ?

Yes. You can also declare constants, procedures, types or anything else in the body too.
What is important to remember here is scope. Anything declared only inside the body is only visible inside the package body, Not to anyone calling:

use my_lib.my_package.all;

This can be useful if you have some utility function that is used inside several of the functions declared in the package declaration.