rakeshk.r
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Hi,
The code below should perform 5.25/3 = 1.75 But i am not getting 1.75 (in signed binary "000111000000000000") instead i am getting "000000000000000001"and I don't why I am getting a wrong output. Also I am aware this code is not for synthesis. Any help to get the correct output is greatly appreciated. Thank you.
---------- my testbench ----------
The code below should perform 5.25/3 = 1.75 But i am not getting 1.75 (in signed binary "000111000000000000") instead i am getting "000000000000000001"and I don't why I am getting a wrong output. Also I am aware this code is not for synthesis. Any help to get the correct output is greatly appreciated. Thank you.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY test_hdl1 IS
port ( clk : IN std_logic;
rst : IN std_logic;
output : OUT signed (17 downto 0)
);
END ENTITY test_hdl1;
--
ARCHITECTURE logic OF test_hdl1 IS
BEGIN
testing :process (clk)
variable reg10: signed (17 downto 0);
variable reg8 : signed (17 downto 0);
variable reg9 : signed (17 downto 0);
begin
if (rising_edge(clk)) then
if (rst='0') then
reg10 := reg8/reg9; -- (4Int,14Fract)
else
reg8 := "010101000000000000";-- 5.25 (4Int,14Fract)
reg9 := "001100000000000000";-- 3 (4Int,14Fract)
reg10 := (others=>'0');
end if;
output <= reg10;
end if;
end process;
END ARCHITECTURE logic;---------- my testbench ----------
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY project_lib;
ENTITY tb_test_hdl1 IS
END ENTITY tb_test_hdl1;
--
ARCHITECTURE logic OF tb_test_hdl1 IS
-- internal signal --
signal clk_tb : std_logic := '0';
signal rst_tb : std_logic := '1';
signal out_tb : signed(17 downto 0);
constant clk_period : time := 10 ns;
-- component instantiation --
component test_hdl1
port(
clk : IN std_logic;
rst : IN std_logic;
output: OUT signed(17 downto 0)
);
end component;
For all : test_hdl1 use entity project_lib.test_hdl1;
BEGIN
uut:test_hdl1 port map(
clk => clk_tb,
rst => rst_tb,
output => out_tb
);
clk_toggle:process
begin
clk_tb <= '1';
wait for clk_period/2;
clk_tb <= '0';
wait for clk_period/2;
end process;
sim_tb: process
begin
rst_tb <= '1';
wait for 10 ns;
rst_tb <= '0';
wait;
end process;
END ARCHITECTURE logic;
