This is an odd quirk from VHDL that annoys most verilog users.
The solution is to create a signal inside your design, eg "cout_buf" and then assign "cout <= cout_buf;".
there are also ways to use a port type of "buffer", but this has other issues when connecting modules, so it is best just to use the extra signal method.
I suggest _buf as the suffix. _i and _int are also common (for "internal"), but also are common for "input" or "integer". Of course _buf might imply an IO buffer...