VHDL or Verilog - Which way to go?

[Jennifer Dsouza]

I have an option to choose between Verilog and VHDL to implement logic gates for now. I have checked around, but do not understand what people mean by saying that VDHL is verbose and Verilog is not. I had also read that VHDL is "very deterministic" and Verilog is "only deterministic if you follow some rules carefully". If someone would please explain this a bit. Also, I have a strong background in C/C++ so I would assume Verilog is a good way to start. Would this be a good choice? If time permits, I may learn both, but for now I need to choose one.
Thanks.

 

[sharath666]

If you have a background in C, then go with verilog. Understand the nuances of the language properly. Then start with learning VHDL.

 

[TrickyDicky]

Choosing a language is a bit of a false start. You really need to understand the underlying logic. If you understand the logic, then understanding either language is possible. Both languages will give the same results when written well, and both can be written very badly, using software constructs that produce terrible logic or just will not compile at all.

Syntactically, you may prefer verilog as its syntax is closer to C than vhdl, but as a programmer you are going to find both languages alien.

- - - Updated - - -

As an addition: There are more free tools for verilog. But vhdl is a better self contained language with more verification features than pure verilog. For better verification you need to learn system verilog which adds lots more complication.

 

[Dan Mills]

Coming from a c background I would actually go for VHDL, simply because verilog is superficially rather too close to c, and tends to encourage you to make assumptions that are valid for c but very wrong (or at least are horrible style) in a hardware definition language.

The point is that in a hardware description language you are NOT programming you are describing how hardware should work, it is the difference between telling a machine what to do and telling it what to be, and it is fundamental.

VHDL is also MUCH more strongly typed then verilog, which while it can be a pain is actually very helpful in a lot of ways.

Regards, Dan.

 

[mrflibble]

Coming from a c background I would actually go for VHDL, simply because verilog is superficially rather too close to c, and tends to encourage you to make assumptions that are valid for c but very wrong (or at least are horrible style) in a hardware definition language.

Precisely this. You see that sort of thing all the time in this forum. So from the familiarity point of view you might actually be better of with vhdl than with verilog, because vhdl has less in common with C than does verilog.

That said I'm not so sure I agree with the "VHDL is more self contained" for verification bit by TrickyDicky. How is VHDL more self contained for verification? Quite often when I read something VHDL related they use something like e or vera or systemverilog for verification. From the verification angle I'd sooner advise to use verilog, because that way you can use systemverilog for your verification. You could even use systemverilog for your design. And lets put it another way, AFAIK there are a lot more designs that have RTL in VHDL and verification in (system)verilog than the other way around.

As for strong typing, yup vhdl is definitely more strongly typed which is a good thing IMO. The drawback however is that vhdl also is a lot more verbose. Soooo, pick your poison.

 

[dave_59]

There is a lot more than just the technical merits of each language when choosing it for design. Will you be integrating your design with anyone else? Do you plan on hiring additional resources in the future? If so what skill are available in your area? Do you plan on acquiring other IP, and what languages is it available in?

Finally, if you want to take advantage of any of the complex testbench features of SystemVerilog, you may want to chose Verilog for your design to make it easier to transition from design to verification.

 

[shaiko]

I'd base my choice on whatever more commonly used by the industry in the place you live.
With that said - as TrickyDicky noted, "what language" is a secondary thing. First you should get very familiar with digital logic and remember that (any) HDL is only a tool for describing it.

 

[TrickyDicky]

Precisely this. You see that sort of thing all the time in this forum. So from the familiarity point of view you might actually be better of with vhdl than with verilog, because vhdl has less in common with C than does verilog.

That said I'm not so sure I agree with the "VHDL is more self contained" for verification bit by TrickyDicky. How is VHDL more self contained for verification? Quite often when I read something VHDL related they use something like e or vera or systemverilog for verification. From the verification angle I'd sooner advise to use verilog, because that way you can use systemverilog for your verification. You could even use systemverilog for your design. And lets put it another way, AFAIK there are a lot more designs that have RTL in VHDL and verification in (system)verilog than the other way around.

As for strong typing, yup vhdl is definitely more strongly typed which is a good thing IMO. The drawback however is that vhdl also is a lot more verbose. Soooo, pick your poison.

Basically there's a lot you can do with vhdl that you cannot with pure verilog, you need sv. But because sv has industry adoption it has a lot more created for it (eg uvm) it would be silly not to choose it now.

E and Vera are a bit more proprietry than sv, so I've never seen their use. But where I currently work vhdl is used for implementation and sv used for higher level verification. But some very complicated vhdl test benches have been built.

 

[Serwan Bamerni]

Ok can I ask a question
some people said that the future is for verilog especially after the appear of systemverilog
and VHDL will decay in the next near years
is that true?

 

[shaiko]

Ok can I ask a question
some people said that the future is for verilog especially after the appear of systemverilog
and VHDL will decay in the next near years
is that true?

Probably not in the "next near years" and probably not decay completely - it just seems like there isn't going to be any further development in VHDL.

With that said, it's still going to be used a lot in the foreseeable future.

 

[TrickyDicky]

Ok can I ask a question
some people said that the future is for verilog especially after the appear of systemverilog
and VHDL will decay in the next near years
is that true?

Ive heard this story ever since Ive been in the industry for over 10 years. 10 years a go the big story was C to gates synthesis (thats now pretty dead) and a few years ago a big song and dance was made of Simulink having HDL coder and Xilinx and Altera creating their own versions (something from Xilinx and DSP builder from Altera). They seem rather quite now too. Now the new fads are HDS and OpenCL.

VHDL is still here and still being developed. Remember there is a large amount of legacy VHDL will still need supporting.

It is true that the Verification ships have all sailed and it appears everyone is on board the SV ship. But for synthesis SV is still not supported by all tools.

 

[shaiko]

VHDL is still here and still being developed

It's very much here...but: "being developed" ? How?
It has been 6 years since the VHDL IEEE 1076-2008 standart came out and it still doesn't have reliable tool support.

 

[TrickyDicky]

It's very much here...but: "being developed" ? How?
It has been 6 years since the VHDL IEEE 1076-2008 standart came out and it still doesn't have reliable tool support.

Mis-worded. I meant people are developing with it.
The newest development will be OSVVM - but thats not part of the VHDL standard (but probably will be part of a newer revision - but that is many years away, if ever)

 

[std_match]

National Instruments put more and more user-programmable FPGA's in their hardware. The top must be in LabView but sub-blocks can be designed in VHDL. The LabView subset for FPGA design is compiled to VHDL (encrypted). Verilog is not supported, but it is possible to import netlists created by other tools. The VHDL code plus imported netlists are sent to the Xilinx tools for bitfile generation.