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| library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity multiplier is
port(clr,load_a, load_b,sf_b,ld_p,sf_p,clk: in std_logic;
P: out std_logic_vector(7 downto 0));
end multiplier;
architecture beh of multiplier is
component dffa
port(din:in std_logic_vector(3 downto 0);
clr,clk,load:in std_logic;
q: out std_logic_vector(3 downto 0));
end component;
component dffb
port(d: in std_logic_vector(3 downto 0);
clk,load,clr, sb: in std_logic;
qb0: out std_logic);
end component;
component mux
port(d0, d1 :in std_logic_vector(3 downto 0);
s: in std_logic;
y: out std_logic_vector(3 downto 0));
end component;
component adder
port(a, b :in std_logic_vector(3 downto 0);
res: out std_logic_vector(4 downto 0));
end component;
component product
port(sum:in std_logic_vector(4 downto 0);
clr,clk,sb, load:in std_logic;
Ph: out std_logic_vector(3 downto 0);
Remain: out std_logic_vector (3 downto 0));
end component;
component product2
port(Pcar:in std_logic_vector(3 downto 0);
clk:in std_logic;
Pl: out std_logic_vector(3 downto 0));
end component;
signal A_reg,Zero,Y1, remainder, Preg, PP, Pr: std_logic_vector(3 downto 0);
signal Addsum5: std_logic_vector(4 downto 0);
signal carry: std_logic;
signal A,B: std_logic_vector (3 downto 0);
begin
A <= "1011";
B <= "1101";
Zero <= "0000";
--remainder <= "0000";
g0: dffa port map(din => A, clr => clr, clk => clk, load => load_a, q => A_reg);
g1: dffb port map(d => B, clk => clk, load => load_b, clr=> clr, sb => sf_b, qb0 => carry);
g2: mux port map(d0 => Zero, d1 => A_reg,s => carry, y=> Y1);
g3: adder port map(a => Y1, b=> remainder, res => Addsum5);
g4: product port map(sum => Addsum5, clr => clr, clk => clk, sb => sf_p, load => ld_p, Remain => remainder, Ph => Preg);
g5: product2 port map(Pcar => remainder, clk => clk, Pl => PP);
process(clr,load_a, load_b,sf_b,ld_p,sf_p,clk)
begin
if(clr = '1') then
P <= (others => '0');
elsif(rising_edge(clk)) then
if(load_a = '1') then
A_reg <= A(3 downto 0);
elsif(load_b = '1') then
B <= B(3 downto 0);
elsif(sf_b = '1') then
remainder <= "0000";
elsif(ld_p = '1') then
remainder <= Addsum5(4 downto 1);
elsif(sf_p = '1') then
Pr <= '0'& Addsum5(3 downto 1);
PP <= Pr(3 downto 0);
end if;
end if;
end process;
P(7 downto 4) <= Pr;
P(3 downto 0) <= PP;
end beh; |