[VHDL+ModelSim] ModelSim and FSM

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vhdl conv_integer with select

Can I see with Modelsim state of my FSM, if state is :

architecture

type state_t is (st0, st1, st2 st3);

signal state : state_f;

?

How can I write my ports entity, if my signal is TYPE OF ???

thanks
 

fsm modelsim error vhdl type

"state" is just a signal. So you can add it in signal list in ModelSim and view its behavior during simulation. (I suppose there is a synthax error in your post - signal state : state_t;<- not state_f)
 

std_logic_vector resolves to x in modelsim

I can't find it ... because synthesis change the variables and don't contains the same significant value... There's another method ?

thanks
 

fsm list modelsim

ModelSim is a simulation tool, not synthesis. Custom usage - functional simulation. Also exists opportunity of post-fitting simulation (based on .vho files, for example). But after synthesis, "state" signal will be unavailable.

If you use only functional simulation, then state_t must be present in the signal list after compilation. All signals are available for simulation (in conyrast of variables).

P.S.: If it is possible, attach your code here.
 

If I use functional simulation, I have a problem to use CONV_INTEGER to convert my integer counter to a std_logic_vector... How can I resolve this problem (leaving Integer variable)? I must import any library ?

My project is Full of CONV_INTEGER...

Modelsim give me this error :
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 622200 ps Iteration: 1 Instance: /chx_cu_tb/uut
 

Problems in convertion integers to std_logic_vector?
Try this code:

Code: 
  FUNCTION  to_vector(input,num_bits:integer) RETURN std_logic_vector IS
    VARIABLE result:std_logic_vector(num_bits-1 DOWNTO 0);
    VARIABLE weight:integer;
    VARIABLE temp:integer;
  BEGIN
    weight := 2**(num_bits-1);
    temp := input;
    FOR i in result'HIGH DOWNTO result'LOW LOOP
      IF temp >= weight THEN
        result(i) := '1';
        temp := temp - weight;
      ELSE
        result(i) := '0';
      END IF;
      weight := weight/2;
    END LOOP;
    RETURN result;
  END to_vector;

And as for warning - it seems that the result of arithmetic operation is unknown (because one of operand is 'U'|'X'|'W'|'Z'). So ModelSim determine the result as UNKNOWN - ('X'). It is difficult to say something more without having source code.
 

This is a sample of code .... I have problem to do a Functional Simulation :

WHY ???


Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity buffer_fifo_32bit is
  Port ( 
	  clk      : in  std_logic;
	  rst      : in  std_logic;

	  put_data : in  std_logic;
          get_data : in  std_logic;
	  empty    : inout std_logic;
	  full 	   : inout std_logic;
	  
          data_in  : in  std_logic_vector (0 to 31);
          data_out : out std_logic_vector (0 to 31));

end buffer_fifo_32bit;

architecture arch_32bit of buffer_fifo_32bit is

  component ram_dualport is
      Port ( clk : in std_logic;

             we : in std_logic;
             data_in : in std_logic_vector(0 to 31);
             W_add : in std_logic_vector(7 downto 0);

             R_add : in std_logic_vector(7 downto 0);
             data_out : out std_logic_vector(0 to 31));
  end component;

  signal addr_out   : std_logic_vector (7 downto 0) := "00000000";
  signal addr_in    : std_logic_vector (7 downto 0) := "00000000";
  signal nelementi  : std_logic_vector (7 downto 0) := "00000000";
  signal we         : std_logic;

begin

	with nelementi select
		empty <= '1' when "00000000",
			    '0' when others;
	
	with nelementi select
		full  <= '1' when "11111111",
			    '0' when others;

	buffer_u1: process (clk, rst, addr_in, addr_out, nelementi, get_data, put_data) 
	  variable v_addr_in, v_addr_out, v_nelementi : std_logic_vector (7 downto 0);
	begin
		if (rst = '1') then
		  v_addr_in	:= (OTHERS => '0');
		  v_addr_out	:= (OTHERS => '0');			
		  v_nelementi	:= (OTHERS => '0');
		  addr_in	<= (OTHERS => '0');
		  addr_out	<= (OTHERS => '0');			
		  nelementi	<= (OTHERS => '0');

		elsif (rising_edge(clk)) then
		  if (put_data = '1' AND full='0') then
		    v_addr_in := v_addr_in + "00000001";
		    v_nelementi := v_nelementi + "00000001";
		  else
		    v_addr_in := v_addr_in;				
		  end if;
		
		  if (get_data = '1' AND empty='0') then
		    v_addr_out := v_addr_out + "00000001";
		    v_nelementi := v_nelementi - "00000001";
		  else
		    v_addr_out := v_addr_out;
		  end if; 

		  addr_in <= v_addr_in;
		  addr_out <= v_addr_out;
		  nelementi <= v_nelementi;
		end if;	

	end process;

	we <= put_data;
	ramdualport : ram_dualport port map (clk => clk, data_in => data_in, we => we, W_add => addr_in, R_add => addr_out, data_out => data_out);

end arch_32bit;

------------------- cut Here ---------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram_dualport is
    Port ( 
          clk : in std_logic; we : in std_logic;           
	  data_in : in std_logic_vector(31 downto 0);
          W_add : in std_logic_vector(7 downto 0);
           
	  R_add : in std_logic_vector(7 downto 0);
          data_out : out std_logic_vector(31 downto 0));
end ram_dualport;

architecture architecture_256x32 of ram_dualport is

  type ram is array (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (31 downto 0);
  signal ram_256 : ram (0 to (2**8));

begin

  ram_dualport: process (clk,R_add) 
  begin
    if ( rising_edge(clk) ) then
      if (we = '1') then
        ram_256(conv_integer(W_add)) <= data_in;
      end if;
    data_out <= ram_256(conv_integer(R_add));
    end if;
          
  end process;
	
end architecture_256x32;

Modelsim give me an U output to data_out... with this error

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 12200 ps Iteration: 1 Instance: /buffer_fifo_32bit_tb/uut/ramdualport
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 12200 ps Iteration: 1 Instance: /buffer_fifo_32bit_tb/uut/ramdualport
# ** Failure: Simulation successful (not a failure). No problems detected.
# Time: 134400 ps Iteration: 0 Process: /buffer_fifo_32bit_tb/line__77 File: buffer_fifo_32bit_tb.vhw


Why ???
If I try with synthesys simulation, I receive an good responce....
 

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