Receiving and sending formatted numbers through an UART isn't a natural FPGA design task, but it's possible to perform the job of course. You'll implement a FSM (respectively multiple nested FSM) to do the character reception, number decoding and store to BRAM.
It sounds like you also want readable terminal output from the FPGA. Does this involve decimal number formatting? Or is hexadecimal format acceptable, which can be generated with less effort.
Most of the design planning isn't directly related to FPGA and VHDL, e.g. defining the in- and output UART data formats, sketching state diagrams of the data processing.