VHDL Matrix Multiplication using UART and BRAM

[maha_66]

My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA device receives data and operates (add or mult) on the two matrices and sends back the output (16) using the UART Tx and the output matrix is shown on the terminal. I am still in the design process.

1) How to input the matrix for multiplication or addition using the terminal?

2) How to use the BRAMs to receive the two matrices for the terminal?

3) Since I don't need to initialize BRAMs from an external file, how do I make it recieve data using the UART?

 

[barry]

You mean you want us to do the design for you?

1) the terminal sends data to the UART. When you receive data you store it in bram.
2) see 1)
3 ) see 2)

Honestly, ask a more specific question. you've shown absolutely no effort in this task.

 

[maha_66]

The questions I asked were mainly to validate whether I was thinking in the right direction.
My main concern was how do I accept input from terminal as a single string that define the num. of rows and columns of two matrices. I do not need your insight on how much effort I have put in. You can either be helpful or not respond at all.

 

[FvM]

Receiving and sending formatted numbers through an UART isn't a natural FPGA design task, but it's possible to perform the job of course. You'll implement a FSM (respectively multiple nested FSM) to do the character reception, number decoding and store to BRAM.

It sounds like you also want readable terminal output from the FPGA. Does this involve decimal number formatting? Or is hexadecimal format acceptable, which can be generated with less effort.

Most of the design planning isn't directly related to FPGA and VHDL, e.g. defining the in- and output UART data formats, sketching state diagrams of the data processing.

 

[maha_66]

Thank you for making it clearer. It does not involve decimal formatting. Hex format is acceptable.