Kamran Saleh
Newbie level 2
Dear Friends,
I have used the following VHDL expression to divide an integer by a constant power of 2 and simulated the code with Modelsim 6.0:
signal a,b: integer range -1024 to 1023;
a <= b / 128;
it works properly with positive numbers. surprisingly, when b is a negative number, some times the result is not correct. for example if b=-256 then a = -2 (correct). but when b = -300 then a = -2 instead of -3. In other words the simulator rounds the result toward zero instead of calculating the FLOOR of the result.
if i define a and b as std_logic_vector and use a right shift instead of the '/' operator, the result is -3 (OK).
My question: is there any way for dividing an integer by a constant power of 2 numbers?