VHDL Integer Division Problem

[Kamran Saleh]

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Dear Friends,

I have used the following VHDL expression to divide an integer by a constant power of 2 and simulated the code with Modelsim 6.0:

signal a,b: integer range -1024 to 1023;

a <= b / 128;

it works properly with positive numbers. surprisingly, when b is a negative number, some times the result is not correct. for example if b=-256 then a = -2 (correct). but when b = -300 then a = -2 instead of -3. In other words the simulator rounds the result toward zero instead of calculating the FLOOR of the result.

if i define a and b as std_logic_vector and use a right shift instead of the '/' operator, the result is -3 (OK).
My question: is there any way for dividing an integer by a constant power of 2 numbers?

 

[FvM]

In other words the simulator rounds the result toward zero instead of calculating the FLOOR of the result.

Do you know a language specification that makes you expect floor as result of integer division?

I see the following language specfication in IEEE Std 1076, 7.2.6

Integer division satisfies the following identity:
(–A)/B = –(A/B) = A/(–B)

P.S.: You get in fact a different result on right shift of signed numbers in 2s complement representation. While VHDL has an explicite specification for the behaviour of negative integers in division, you'll find that the result is usually specified "implementation dependent" with programming languages like C. This may give the appearance, that the usually observed behaviour caused by 2s complement representation is "natural". But it isn't. In other words, the "integer division problem" reveals as a problem of inappropriate expectations.

 

[TrickyDicky]

You have to remember, integers are not bit vectors in VHDL. so their behaviour is defined by the language, not the bitwise arithmatic.

 

[Kamran Saleh]

Thanks a lot