Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Library ieee; use ieee.std_logic_1164.all; entity PowerSeq is port(fpga_clk: in std_logic; Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic; PG_3V3: in std_logic); end PowerSeq; architecture MPU_PowerSeq of PowerSeq is signal pon_state: integer:= 0; begin process(fpga_clk) begin if(rising_edge(fpga_clk)) then if(pon_state = 0) then Enable_3V3 <= '1'; Enable_1P5V <= '1'; Enable_1V <= '0'; Enable_Bias_1V <= '1'; pon_state <= 1; end if; if(pon_state = 1) then if(PG_3V3 = '1') then Enable_1V <= '1'; end if; end if; end if; end process; end MPU_PowerSeq;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity PowerSeq is end PowerSeq; architecture MPU_PowerSeq of PowerSeq is component Sequence is port(fpga_clk : in std_logic; Reset: in std_logic; Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic; PG_3V3: in std_logic); end component; signal Reset: std_logic:= '0'; signal fpga_clk : std_logic:= '0'; signal Enable_Bias_1V: std_logic:= '0'; signal Enable_3V3: std_logic:= '0'; signal Enable_1P5V: std_logic:= '0'; signal Enable_1V: std_logic:= '0'; signal pon_state: integer:= 0; signal PG_3V3: std_logic:= '0'; constant tb_time: time:= 15.5 ns; begin uut: sequence port map( Reset => Reset, fpga_clk => fpga_clk, Enable_Bias_1V => Enable_Bias_1V, Enable_3V3 => Enable_3V3, Enable_1P5V => Enable_1P5V, Enable_1V => Enable_1V, PG_3V3 => PG_3V3 ); stimlus: process begin fpga_clk <= '0' after tb_time, '1' after 2 * tb_time; wait for 2 * tb_time; end process; tb: process begin wait for 50 ns ; Reset <= '0'; Enable_Bias_1V <= '0'; Enable_3V3 <= '0'; Enable_3V3 <= '0'; Enable_1V <= '0'; wait for 50 ns; Reset <= '1'; wait for 1 us; end process; end;
What exactly are you expecting to see? the UUT is clearly not the same as the code you posted - it is a different named entity (PowerSeq in code, Sequence in testbench) and it has a different port map (PowerSeq has no reset port).
So, why not post the code thats actually being simulated?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Library ieee; use ieee.std_logic_1164.all; entity PowerSeq is port(fpga_clk,Reset: in std_logic; Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic; PG_3V3, PG_1V: in std_logic); end PowerSeq; architecture MPU_PowerSeq of PowerSeq is signal pon_state: integer:= 0; begin process(fpga_clk) begin if(rising_edge(fpga_clk)) then if(reset = '1') then Enable_3V3 <= '0'; Enable_1P5V <= '0'; Enable_1V <= '0'; Enable_Bias_1V <= '0'; end if; if(pon_state = 0) then Enable_3V3 <= '1'; Enable_1P5V <= '1'; Enable_1V <= '0'; Enable_Bias_1V <= '1'; pon_state <= 1; end if; if(pon_state = 1) then if(PG_3V3 = '1') then Enable_1V <= '1'; end if; end if; end if; end process; end MPU_PowerSeq;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity PowerSeq is end PowerSeq; architecture MPU_PowerSeq of PowerSeq is component PowerSeq is port(fpga_clk : in std_logic; Reset : in std_logic; Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic; PG_3V3 : in std_logic ); end component; signal Reset : std_logic:= '0'; signal fpga_clk : std_logic:= '0'; signal Enable_Bias_1V : std_logic:= '0'; signal Enable_3V3 : std_logic:= '0'; signal Enable_1P5V : std_logic:= '0'; signal Enable_1V : std_logic:= '0'; signal pon_state : integer:= 0; signal PG_3V3 : std_logic:= '0'; constant tb_time : time:= 1 ns; begin --sim:/powerseq uut: PowerSeq port map( Reset => Reset, fpga_clk => fpga_clk, Enable_Bias_1V => Enable_Bias_1V, Enable_3V3 => Enable_3V3, Enable_1P5V => Enable_1P5V, Enable_1V => Enable_1V, PG_3V3 => PG_3V3 ); stimlus: process begin fpga_clk <= '0' after tb_time, '1' after 2 * tb_time; wait for 2 * tb_time; end process; tb: process begin wait for 5 ns ; Reset <= '0'; Enable_Bias_1V <= '1'; Enable_3V3 <= '1'; Enable_1P5V <= '1'; wait for 5 ns; if(pon_state = 0) then Enable_Bias_1V <= '1'; Enable_3V3 <= '1'; Enable_1P5V <= '1'; pon_state <= 1; end if; if(pon_state = 1) then PG_3V3 <= '1'; Enable_1v <= '1'; end if; -- wait for 5 ns; --Reset <= '1'; end process; end;
Im surprised you got this to work, as your testbench has the same entity name as the UUT.
You also seem to be driving outputs from the UUT in the testbench, so I dont beleive the wave form you shows is from simulating any code you have posted.
Please find out exactly what you are simulating, and post it.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 library ieee; use ieee.std_logic_1164.all; entity powering is port(fpga_clk,Reset: in std_logic; Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic; PG_3V3, PG_1V: in std_logic); end powering; architecture behavioral of powering is signal pon_state : integer := 0; begin process(fpga_clk) begin if(rising_edge(fpga_clk)) then if(pon_state=0) then Enable_3V3 <= '1'; Enable_1P5V <= '1'; Enable_Bias_1V <= '1'; pon_state <= 1; end if; if(pon_state = 1) then if(PG_3V3 = '1') then Enable_1V <= '1'; end if; end if; end if; end process; end behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity sequence is end sequence; architecture behav of sequence is component powering port( Reset: in std_logic:= '0'; fpga_clk : in std_logic:= '0'; Enable_3V3 : out std_logic:= '0'; Enable_1p5V: out std_logic:= '0'; Enable_1V: out std_logic:= '0'; Enable_Bias_1V : out std_logic:= '0'; PG_3V3: in std_logic:= '0'); end component; signal Reset: std_logic:= '0'; signal fpga_clk : std_logic:= '0'; signal Enable_Bias_1V: std_logic:= '0'; signal Enable_3V3: std_logic:= '0'; signal Enable_1P5V: std_logic:= '0'; signal Enable_1V: std_logic:= '0'; signal pon_state: integer:= 0; signal PG_3V3: std_logic:= '0'; constant tb_time: time:= 1 ns; begin uut: powering port map ( Reset => Reset, fpga_clk => fpga_clk, Enable_Bias_1V => Enable_Bias_1V, Enable_3V3 => Enable_3V3, Enable_1P5V => Enable_1P5V, Enable_1V => Enable_1V, PG_3V3 => PG_3V3 ); stimuls: process begin fpga_clk <= '0' after tb_time, '1' after 2 * tb_time; wait for 2 * tb_time; end process; tb: process begin wait for 5 ns; Reset <= '1'; Enable_Bias_1V <= '0'; Enable_3V3 <= '0'; Enable_1P5V <= '0'; Enable_1V <= '0'; Enable_Bias_1V <= '0'; wait for 5 ns; PG_3V3 <= '1'; Enable_1V <= '1'; end process; end;
The latest code you posted in post #5 has a missmatch between the "powering" entity and "powering" component. the entity has a port called PG_1V and the component does not, so you cannot map the component to the entity (you get a compile/mapping error).
So what you have posted clearly is NOT what you have tried to simulate or compiled, as it will not compile for me.
The fact you have posted 3 different sets of code that ALL have this problem, I suspect your project is a bit of a mess. Please tidy it up.
IS there any issue other than this PG_1V?
Yes, you are driving the outputs of the UUT, so you will get X's in the testbench if the UUT drives '0' and the TB drives '1' (or vice versa)
Why are you driving the outputs of the UUT from the testbench?
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