karansinghdx
Newbie level 3
Hey, I have this clock code with me, which is working
entity digi_clk is
port (clk1 : in std_logic;
clk : out std_logic
);
end digi_clk;
architecture Behavioral of digi_clk is
signal count : integer :=1;
--signal clk : std_logic :='0';
begin
--clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
What I want are 2 more outputs
1) which becomes high only when count is 1
2) other becomes high only when the count value is 500000000
I am getting so much problems getting only these 2 output signals, it seems easy but somehow I am not able to do it.
Help please.
entity digi_clk is
port (clk1 : in std_logic;
clk : out std_logic
);
end digi_clk;
architecture Behavioral of digi_clk is
signal count : integer :=1;
--signal clk : std_logic :='0';
begin
--clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
What I want are 2 more outputs
1) which becomes high only when count is 1
2) other becomes high only when the count value is 500000000
I am getting so much problems getting only these 2 output signals, it seems easy but somehow I am not able to do it.
Help please.