franticEB
Full Member level 3

Hi i've to realize in vhdl the scheme in figure

In FPGA there is a block that reads from input port and stores in its internal register a certain value; i want to use this port as output for 2 spi module as in figure.
I try to implement in vhdl the scheme as in figure but altera quartus II cannot synthesize givin me the following error:
Error (13076): The node "XXXXXX" has multiple drivers due to the non-tri-state driver"
the code is below:
Anyone could help me?

In FPGA there is a block that reads from input port and stores in its internal register a certain value; i want to use this port as output for 2 spi module as in figure.
I try to implement in vhdl the scheme as in figure but altera quartus II cannot synthesize givin me the following error:
Error (13076): The node "XXXXXX" has multiple drivers due to the non-tri-state driver"
the code is below:
Code:
INOUT_PORT <= spi_wire when enb='1' else 'Z';
spi_wire <= out_spi_1 when select='1' else out_spi_2;
reader_wire <= INOUT_PORT when enb='0' else 'Z';
Anyone could help me?