[SOLVED] vhdl inout port reading writing

[franticEB]

Hi i've to realize in vhdl the scheme in figure



In FPGA there is a block that reads from input port and stores in its internal register a certain value; i want to use this port as output for 2 spi module as in figure.
I try to implement in vhdl the scheme as in figure but altera quartus II cannot synthesize givin me the following error:

Error (13076): The node "XXXXXX" has multiple drivers due to the non-tri-state driver"

the code is below:

INOUT_PORT <= spi_wire when enb='1' else 'Z';

spi_wire <= out_spi_1 when select='1' else out_spi_2;

reader_wire <= INOUT_PORT when enb='0' else 'Z';

Anyone could help me?

 

[FvM]

There are no multiple drivers in the shown code snippet, but a meaningless internal tri-state and illegal usage of a reserved name "select" for a signal. The latter makes me think that you didn't post the actual code.

Why not simply writing:

INOUT_PORT <= 'Z' when enb = '0' else
   out_spi_1 when sel = '1' else 
   out_spi_2;
reader_wire <= INOUT_PORT

 

[franticEB]

There are no multiple drivers in the shown code snippet, but a meaningless internal tri-state and illegal usage of a reserved name "select" for a signal. The latter makes me think that you didn't post the actual code.

Why not simply writing:

INOUT_PORT <= 'Z' when enb = '0' else
   out_spi_1 when sel = '1' else 
   out_spi_2;
reader_wire <= INOUT_PORT

This code doesn't resolve my problem. I can view rtl schematic but the design doesn't pass the synthesis phase with the same error:

"The node "INOUT" has multiple drivers due to the non-tri-state driver"

more precisely

"The node "INOUT" has multiple drivers due to the non-tri-state driver of out_spi_1 port"

 

[FvM]

This code doesn't resolve my problem.

You didn't actually report the problem. The code compiles correctly as such.

To get any help, you should show a complete entity that reproduces the problem.

 

[af_bln]

It seems you are going to serve the data from two different sources. For this case I guess you have to use an interstage.
Something like this:

out_spi <= out_spi_1 when sel = '1' else out_spi_2;

INOUT_PORT <= 'Z' when enb = '0' else out_spi;
reader_wire <= INOUT_PORT

 

[franticEB]

I resolve the problem configuring out_spi_1 and out_spi_2 in high impedance when not in output mode.