library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_driver_v2 is
Port ( clk : in std_logic;
rst : in std_logic;
D7_D0_in : in std_logic_vector (7 downto 0);
empty : in std_logic;
D7_D0_out : out std_logic_vector(7 downto 0);
RS : out std_logic;
EN : out std_logic;
conteggio: out std_logic_vector (15 downto 0));
end lcd_driver_v2;
architecture lcd_driver_arch of lcd_driver_v2 is
type tipo_stato is (stato0,stato1,stato2,stato3,stato4,stato5,stato6,stato7,stato8,stato9);
signal stato : std_logic_vector(3 downto 0);
type rom_array is array (0 to 4) of std_logic_vector (7 downto 0);
constant rom: rom_array := ("00000000",
"00011110",
"00011110",
"00011110",
"00111000");
signal clk_200u : std_logic;
begin
U1_clk_div : process (clk)
variable v_count_clk : INTEGER RANGE 0 to 10001;
begin
if (rising_edge(clk)) then
v_count_clk := v_count_clk + 1;
if (v_count_clk > 10000) then -- if (count = 20001) then
clk_200u <= NOT clk_200u;
v_count_clk := 0;
end if;
end if;
end process;
U2_state_machine : process (stato, clk_200u, rst)
variable v_count : INTEGER;
begin
if (rst = '1') then
D7_D0_out <= "00000000";
RS <= '0';
EN <= '1';
stato <= "0000";
v_count := 0;
elsif (rising_edge(clk_200u)) then
v_count := v_count + 1;
case stato is
when "0000" =>
if (v_count = 76) then
D7_D0_out <= "00000000";
RS <= '0';
EN <= '1';
stato <= "0001";
v_count := 0;
else
D7_D0_out <= "00000000";
RS <= '0';
EN <= '1';
stato <= "0000";
end if;
when "0001" =>
if (v_count = 26) then
D7_D0_out <= "00001111";
RS <= '0';
EN <= '0';
stato <= "0010";
v_count := 0;
else
D7_D0_out <= "00001111";
RS <= '0';
EN <= '1';
stato <= "0001";
end if;
when "0010" =>
if (v_count = 2) then
D7_D0_out <= "00000001";
RS <= '0';
EN <= '0';
stato <= "0011";
v_count := 0;
else
D7_D0_out <= "00000001";
RS <= '0';
EN <= '1';
stato <= "0010";
end if;
when "0011" =>
if (v_count = 2) then
D7_D0_out <= "00111100";
RS <= '0';
EN <= '0';
stato <= "0100";
v_count := 0;
else
D7_D0_out <= "00111100";
RS <= '0';
EN <= '1';
stato <= "0011";
end if;
when "0100" =>
if (v_count = 2) then
D7_D0_out <= "00011100";
RS <= '0';
EN <= '0';
stato <= "0101";
v_count := 0;
else
D7_D0_out <= "00011100";
RS <= '0';
EN <= '1';
stato <= "0100";
end if;
when "0101" =>
if (v_count = 2) then
D7_D0_out <= "00001010";
RS <= '0';
EN <= '0';
stato <= "0110";
v_count := 0;
else
D7_D0_out <= "00001010";
RS <= '0';
EN <= '1';
stato <= "0101";
end if;
when "0110" =>
if (v_count = 2) then
D7_D0_out <= "00000001";
RS <= '0';
EN <= '0';
stato <= "0111";
v_count := 0;
else
D7_D0_out <= "00000001";
RS <= '0';
EN <= '1';
stato <= "0110";
end if;
when "0111" =>
if (v_count = 2) then
D7_D0_out <= "00000111";
RS <= '0';
EN <= '0';
stato <= "1000";
v_count := 0;
else
D7_D0_out <= "00000111";
RS <= '0';
EN <= '1';
stato <= "0111";
end if;
when "1000" =>
if (v_count = 2) then
D7_D0_out <= "00001110";
RS <= '0';
EN <= '0';
stato <= "1001";
v_count := 0;
else
D7_D0_out <= "00001110";
RS <= '0';
EN <= '1';
stato <= "1000";
end if;
when "1001" =>
if (v_count = 2) then
if ( empty = '0' ) then
D7_D0_out <= D7_D0_in;
RS <= '1';
EN <= '0';
stato <= "1001";
v_count := 0;
else
D7_D0_out <= D7_D0_in;
RS <= '1';
EN <= '1';
stato <= "1001";
end if;
else
D7_D0_out <= D7_D0_in;
RS <= '1';
EN <= '1';
stato <= "1001";
end if;
when OTHERS =>
stato <= "0000";
end case;
end if;
conteggio <= CONV_STD_LOGIC_VECTOR(v_count,16);
end process;
end lcd_driver_arch;