The packages declarare operators and functions to use in logic synthesis. To my opinion, STD_LOGIC_1164 and STD_LOGIC_ARITH are the packages that should be suitable for most designs. STD_LOGIC_UNSIGNED could be used additional. It introduces a Verilog similar behavior as all std_logic_vector is also regarded as unsigned number. Personally, I prefer declaring SIGNED and UNSIGNED explicitely, possibly requiring some additional type casts but getting more clarity.