VHDL if generate statement issue

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raghava

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HI all,

GAUSS_33: if (K_SIZE = 3) generate
signal x: std_logic;
begin


end generate GAUSS_33;

Is the signal 'x' is visible to outside of generate statement.
When I use signal 'x' outside, I am getting error message that signal not declared.
How can I do..

Any help is appreciated.

Regards
 

It is now allowed to define a signal inside FOR (or IF) - GENERATE operator.
Just read "VHDL circuit design", by Pedroni, or something like that.
 

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