VHDL if generate statement issue

[raghava]

HI all,

GAUSS_33: if (K_SIZE = 3) generate
signal x: std_logic;
begin


end generate GAUSS_33;

Is the signal 'x' is visible to outside of generate statement.
When I use signal 'x' outside, I am getting error message that signal not declared.
How can I do..

Any help is appreciated.

Regards

 

[dmk]

It is now allowed to define a signal inside FOR (or IF) - GENERATE operator.
Just read "VHDL circuit design", by Pedroni, or something like that.