# VHDL: How to include simulation only signals that can be prevented from synthesizing

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#### matrixofdynamism

When debugging entities, we may create new signals that are only to be used for debug purpose and no intention to actually synthesize them in the final design exists. Is there a way to do this in VHDL such that these signals can be enabled or disabled in synthesis using a single enable variable or with a "touch of a button"? Otherwise one would have to go through all the design entities and remove them manually.

#### FvM

##### Super Moderator
Staff member
Most tools support synthesis attributes for this purpose. Review your documentation.
Code:
-- synthesis translate_off
debug only code
-- synthesis translate_on

The other point to consider is that signals without fanout aren't synthesized. In so far it's not necessarily required to comment all simulation related code.

matrixofdynamism

### matrixofdynamism

Points: 2

##### Super Moderator
Staff member
The other point to consider is that signals without fanout aren't synthesized. In so far it's not necessarily required to comment all simulation related code.

Not required, but very helpful in reducing the number of warnings you have to sift through to make sure the synthesis is clean.

#### matrixofdynamism

WOW. Thankyou so much dude.

Can you give me an example of how to use this?

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##### Super Moderator
Staff member
Can you give me an example of how to use this?
FvM already gave you an example in #2. You just put the code you don't want to synthesize between the commented lines:
Code:
[COLOR="#FF0000"][B]-- synthesis translate_off[/B][/COLOR]
--place the code you don't want in your synthesized design between these two synthesis statements
[COLOR="#FF0000"][B]-- synthesis translate_on[/B][/COLOR]

#### matrixofdynamism

hahaha, I was searching for the debug only code in the VHDL manual. I think that this phrase was some sort of command. Little did I know that the command is the comment itself, rather unusual that is.

#### TrickyDicky

Its not actually part of VHDL. Its a synthesisor directive. synthesis translate_off seems to be well accepted now, but all of these will probabyl work:

--synthesis translate_off
--synopsys translate_off
--pragma translate_off

##### Super Moderator
Staff member
Just don't forget to add the translate_on later on after your debug code.

FYI the synthesis directive is exactly the same in Verilog:

//synthesis translate_off
//synopsys translate_off
//pragma translate_off

But I prefer using `ifdef around debug code as I can also remove it from the simulation if so desired by removing it from the simulators command line without having to modify my code. Trouble is with the synthesis directives the simulator doesn't recognize them and will always compile the debug code even if you don't want it compiled.

Another option (if you're willing to have extra generics in your code for debug purposes) is to add a debug generic to the entity ports and bring it all the way up to the top level entity, where you can have the simulation enable the debug code (by setting the generic at compile time). The debug code is written such that there is a genarate-if structure around it, so it only exists if the debug generic is "true".

Regards

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