[SOLVED] VHDL: How display two variables in one line?

[ebrahimi.khoy]

Hi,

In verilog, several variables and strings can be mixed in display command.
Now, I have two variables named counter and PC and I want to display them in the following format in each cycle:

counter=1 PC=2345
counter=2 PC=2349
...

Any solution?

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I found a solution:

report "Cycle=" & integer'image(counter) & "FETCHC=" & integer'image(conv_integer(unsigned(fe.pc)));