VHDL Help! Unresolved issues!

[richirichard]

Hey there!
Im new to VHDL and im getting "unresolved signal is multiply driven" at --> <-- this line in the code. What does it stand for and how shall i recode to resolve this issue?
Im just coding a 5 bit counter that can count up and down that doesnt pass 0 when its counting down and doesnt pass 31 when counting up with a signal s16 that sets the counter to position 0..


Code;

---

Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity C5b_uds is
    port(upp, ned,clock, s16:in std_logic;
        q:out std_logic_vector(4 downto 0);
        carrry:out std_logic);
end entity C5b_uds;
 
architecture beteende of C5b_uds is
subtype state_type is integer range 0 to 31;
-----------> signal present_state, next_state: state_type; <----------------------
begin
    process(present_state,upp,ned,s16)
        begin
            if (ned = '1' and upp = '1') or (ned = '0' and upp = '0') then
                next_state <= present_state;
            else
                if ned = '0' and upp = '1' then
                    if present_state = 31 then
                        next_state <= present_state;
                    else
                        next_state <= present_state + 1;
                        end if;
                else
                    if ned = '1' and upp = '0' then
                        if present_state = 0 then
                            next_state <= present_state;
                        else 
                            next_state <= present_state - 1;
                        end if;
                    end if;
                end if;
            end if;
        end process;
    q<=conv_std_logic_vector(present_state,5);
    state_register:process(clock)
    begin
        if rising_edge(clock) then
            if s16 = '0' then
                next_state <= 16;
            else
            present_state <= next_state;
            end if;
        end if;
    end process;
end architecture beteende;

---

 

[aruipksni]

the probelm is in :

next_state <= 16;

 

[SynthWorks]

Think of each separate process or separate signal assignment (when done concurrently in the architecture) as a separate piece of hardware. Then the multiple driver warning tells you that you have two separate pieces of hardware driving the same output - something we do not do inside of FPGA/ASIC because we don't have (or don't like to use) internal tristates.

As @aruipksni pointed out, the problem is that your "state_register" process drives the next_state signal when it probably intended to only drive the present_state signal.

 

[richirichard]

Think of each separate process or separate signal assignment (when done concurrently in the architecture) as a separate piece of hardware. Then the multiple driver warning tells you that you have two separate pieces of hardware driving the same output - something we do not do inside of FPGA/ASIC because we don't have (or don't like to use) internal tristates.

As @aruipksni pointed out, the problem is that your "state_register" process drives the next_state signal when it probably intended to only drive the present_state signal.

Yeah, thats right. I changed it to present_state <= 16;
but now when i simulate the code the signal s16 doesnt seem to do anything? How do i fix this?

Thanks alot for all the help by the way!

- - - Updated - - -

Not sure if you can see in the picture but all it seems to do when s16 is 0 is stop counting.
any suggestions?

 

[TrickyDicky]

You shouldnt be assigning next state to present state - this is just going to create latches when you build it (you'll probably see a load of errors about this). I suggest just making it all a single clocked process.

 

[SynthWorks]

@TrickyDicky I don't see any latches on next_state. You would only have latches on next_state if it is not completely specified - which my read says it is.

While, I agree that it would be more readable coded in one process, I hesitate as it does not appear to be the issue here.

What is this waveform captured from? It is clearly incorrect wrt S16. Where is s16 captured from? Can you display the value internal to this block?

 

[TrickyDicky]

Sorry, I wasnt quite reading it correctly (late). No latches should be formed as it doesnt actually set any outputs.

 

[ads-ee]

Oddly nobody seems to care that the OP is writing a simple up/down counter as an FSM.

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Code VHDL - [expand]
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if (s16 = '1') then
  updn_cnt <= 16;  -- or 0 if this is supposed to be "position 0"
elsif (upp = '1' and ned = '0' and updn_cnt < 31) then     -- count up if updn_cnt <31
  updn_cnt <= updn_cnt + 1;
elsif (upp = '0' and ned = '1' and updn_cnt > 0) then   -- count down if updn_cnt >0
  updn_cnt <= updn_cnt - 1;
else                                                    -- don't count when updn_cnt is 0 or 31
  updn_cnt <= updn_cnt;                                 -- or when upp = ned is true
end if;

---

I would use something like this in a clocked process instead of that FSM counter. Does the same thing and is easier to understand and maintain.

 

[SynthWorks]

Based on your simulation I have two guesses.
1) s16 and ned are swapped somewhere in the design or testbench, or
2) the state register was not updated correctly. It should be:

    state_register:process(clock)
    begin
        if rising_edge(clock) then
            if s16 = '0' then
                present_state <= 16;
            else
                present_state <= next_state;
            end if;
        end if;
    end process;