What are the actual period intervals that you want, I think your counters are all cycling on the wrong values, I ran your code and you need to fix your code and add adc_timelog1/2 to the reset.
Your counters are really badly written too. IMO a counter should implement a register who's output is fed back to an add 1 and a compare to terminal count. The compare is used as a select to a mux to either load the add 1 or a 0. I really don't like counter code where someone relies on the language rules for assignment ordering instead of explicitly defining what happens when using an if-elsif-end if structure.
You also seem to have problems with knowing how to count and how to compare count values so things line up properly. I bet you want to have the time_ack pulse with a period of 8192 instead of 8193 like you have done (like I said, you need to learn how to count). FYI if you want to count to ten as a human you count like this: 1,2,3,4,5,6,7,8,9,10, but if you are a piece of silicon and you want to count using binary you'll probably count to ten like this: 0,1,2,3,4,5,6,7,8,9. Notice any differences?
Due to your counting problems you are setting and clearing the bits at the wrong time out of phase with each other as the counters timelog1 and timelog2 are not synchronized with each other. timelog1 cycles on 130 counts, and timelog2 cycles on 66 counts, as you can see these two numbers are not a 2:1 ratio.
Learn how to count and how to write a proper counter. Just look for posts on this subject, I've mentioned how to count correctly on multiple threads.