VHDL functions inside packages

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mahmoudathab

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hi i would like to include this functions in a package and use it in any other design can u please help?

Code VHDL - [expand]
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable bcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;
 
begin
for i in 0 to 7 loop  -- repeating 8 times.
bcd(11 downto 1) := bcd(10 downto 0);  --shifting the bits.
bcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) :='0';
 
 
if(i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(3 downto 0) := bcd(3 downto 0) + "0011";
end if;
 
if(i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(7 downto 4) := bcd(7 downto 4) + "0011";
end if;
 
if(i < 7 and bcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.
bcd(11 downto 8) := bcd(11 downto 8) + "0011";
end if;
 
 
end loop;
return bcd;
end to_bcd
 
Last edited by a moderator:

What's you particularly question? I see, that you have been able to copy the popular "double dabble" code from the internet. (Reference in https://en.wikipedia.org/wiki/Double_dabble)

As far as I see, it's a syntactically correct VHDL function. I assume, it will serve it's purpose.

P.S.:
In addition, you would want to add a standard package header (I guess, you'll find a template in your favourite VHDL text book).
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

package my_bcd is
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector;
end package;

package body my_bcd is
-- your code
end package body my_bcd;
 
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