VHDL function to convert an vector datatype to integer

Is there a function to convert an vector datatype to integer and vice versa.

vhdl conv_integer

Well I don't think there is a ready made function to convert, but you can write down your own easily.
example:

-- Convert a std_logic_vector to an unsigned integer
--
function to_uint (a: std_logic_vector) return integer is
alias av: std_logic_vector (1 to a'length) is a;
variable val: integer := 0;
variable b: integer := 1 ;
begin
for i in a'length downto 1 loop
if (av(i) = '1 ') then -- if LSB is '1 ',
val := vat + b; -- add value for current bit position
end if;
b := b*2; -- Shift left 1 bit
end loop;
return val;
end to_uint;

Click to expand...

Example from "VHDL Made Easy" by Pellerin and Taylor.

p.s. if you find this post of any use to you then kindly do click on the "helped me" icon. Regards, salam.

conv_unsigned vhdl

Std_Logic_Arith

The following functions are contained in the library arith.vhd. To use them,
place the line “USE ieee.std_logic_arith.ALL” at the beginning of your
VHDL design.

FUNCTION Pass(arg, size) Return
· CONV_INTEGER INTEGER INTEGER
· CONV_INTEGER UNSIGNED INTEGER
· CONV_INTEGER SIGNED INTEGER
· CONV_INTEGER STD_ULOGIC SMALL_INT;

· CONV_UNSIGNED INTEGER, INTEGER UNSIGNED;
· CONV_UNSIGNED UNSIGNED, INTEGER UNSIGNED;
· CONV_UNSIGNED SIGNED, INTEGER UNSIGNED;
· CONV_UNSIGNED STD_ULOGIC, INTEGER UNSIGNED;

· CONV_SIGNED INTEGER, INTEGER SIGNED;
· CONV_SIGNED UNSIGNED, INTEGER SIGNED;
· CONV_SIGNED SIGNED, INTEGER SIGNED;
· CONV_SIGNED STD_ULOGIC, INTEGER SIGNED;
· CONV_STD_LOGIC_VECTOR INTEGER, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR UNSIGNED, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR SIGNED, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR STD_ULOGIC, INTEGER STD_LOGIC_VECTOR
· EXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;
· SXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;


/////////////////////////////////////////////////////////////////////////////////////////////

Std_Logic_Unsigned

The following function is contained in the library unsigned.vhd. To use it, place
the line “USE ieee.std_logic_unsigned.ALL” at the beginning of your VHDL
design.
· CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
/////////////////////////////////////////////////////////////////////////////////////////////


Std_Logic_Signed

The following function is contained in the library signed.vhd. To use it, place
the line “USE ieee.std_logic_signed.ALL” at the beginning of your VHDL
design.
· CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
/////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////

u can find all info such as the above in this link:

**broken link removed**


good luck
Salma

conv_signed vhdl

Unfortunately std_logic_arith is obsolute and should no more be used. Instead, numeric_std should exclusively be used.

vhdl conv_signed

ya, use nuemric_std or synopsys lib is good for this conversions