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VHDL foreign language attribute

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syedshan

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Hi all

I was having some minor and trivial issues while simulating using VHDL so I looked for options within VHDL, since it does not support PLI like verilog, hence for simulation and verification not very much powerful, I think(Comment please !)

But later I found the 'FOREIGN attribute for VHDL beginning VHDL from 93...

Although I will do the reading for learning it, when I require, I was just curious is it worhwhile. Since earlier I never heard of this wiht any one and at any forum.

Moreover does simulators and synthesizers support it.

Also what languages can we perform, like only C/verilog or also system-verilog etc.
 

mrflibble

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Not that it answers your question, but with SystemVerilog we now also have DPI. Definitely nicer than the old PLI stuff, as in less work to use and more useful features. yay! :)
 

syedshan

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That is great.
But I need to do know for VHDL :grin:

Although I want to use SystemVerilog for my upcoming project but cannot coz I dont have expensive simulator neither have synthesizers.

But here I also want to ask which language is powerful more

1. VHDL
2. System Verilog


In terms of a). Design implementation b.) Verification and simulation

Note that earlier I used to love verilog since I thought it is much easy, best for beginners etc. and VHDL, although I liked it but I thought is difficult. But now I can never thought to return to verilog, since I think VHDL is way ahead of verilog. Even I was stuck in some simulation cases in VHDL, I opted not to go back to verilog even for simulation

w8ing
 

TrickyDicky

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What are you trying to do? I have never struggled with vhdl, writing many behavioural models for verification. Plus google osvvm for constrained random number generation.
 

FvM

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A straightforward approach would be to review the documentation of your simulator (e.g. ModelSim) for support of 'FOREIGN attribute respectively VHDL to C interface.
 

syedshan

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What are you trying to do? I have never struggled with vhdl, writing many behavioural models for verification. Plus google osvvm for constrained random number generation.

Hi. Now I am done with it, but I am asking for having more grip for simulation. Like previously when I needed to read the file that were in floating point (for simulation) numbers, I could not in VHDL and had to change them to 16-bit integer using matlab first, then read.

Now since I am have done using VHDL, and I later get to know about the 'foreign attribute, hence I just wanted to know about it to get more familiar with VHDL simulation
 

TrickyDicky

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Vhdl has no problem reading floating point, and converting them to binary
 

syedshan

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o really

But I read before that it can only read the integer type...hence I had to work the long channel...also I have to also change the simulation model according to the integer data type :(
 

TrickyDicky

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Vhdl can read any file. Remember textio is just that, text, so you can read any thing you want from the text file as its just a string. The textio packages have procedures to read from that string to any base type (char, string, integer, real, bit, time) and the std_logic_textio package can convert to stdlogic or slv. In vhdl 2008 all standard packages have textio procedures for all types. But a text file is just that, text, so you can convert it however you want.

You don't have to use textio. You can read binary files with vhdl too, but that's where things can get a little muddled between simulators.
 

syedshan

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Hi again

by the way there was one more thing.
I might need it for my future need. If you remember I also asked you this thing earlier as well.

How can we halt simulation in VHDL and then resume it. I know I can halt it using assert, but then cannot resume it.
But this thing can be done using c language. where we can take any input to halt and resume our simulation
 

TrickyDicky

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There is no way to halt it within vhdl. There may be tool commands to do it, plus you can always run for a specified period. I don't really know why it would be useful, i have never needed it. I also don't know about halting C code... How do you do that, other than waiting for some external stimulus.
 

syedshan

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There is no way to halt it within vhdl. There may be tool commands to do it, plus you can always run for a specified period. I don't really know why it would be useful, i have never needed it. I also don't know about halting C code... How do you do that, other than waiting for some external stimulus.


hi. replying quite late.
So this is one sitation...

I made the algo for image processing and then dumpded the data in the DDR3 simulation model.
Later when the 400 files were all writen, with each file having around 100 data items....

then I need to read it back from the DDR3 and save it to another file AND lo and behold....! the file cannot open..(i assereted failure if file do not open)...now now have to start all thing again
for half hour simulation... :(

although there might be something which prevent file from opening, but my point is that if I had some option for halt and begin again then it would save time.
Of course I know that for the RTL compilation is necessary, but what I am talking about is the simulation statemtents, not even simulation models (like of DDR3)

VHDL-2008 added stop and finish procedures.

I will look into it. But currently I am using the -93 version...although I think xilinx ISE also support the 200x as well.
I can try but is it full-proof version since it seems relatively new (just 2008) will the functionalities met by all the compilers and synthesizers?

Thanks
 

TrickyDicky

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I don't quite get it... If the file wont open there's a problem in the testbench. Stopping or assert failure still means you need to restart the whole testbench. So you need t try and work out why it wont open.
 

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