VHDL For Loop Synthesis Problem!

[FuzzySNR]

vhdl for loop

Here's a snapcode of my code, though it simulates OK when I try to synthesize it (Synplify 8.1) I get the following error:

for loops with unbound ranges should contain a wait statement

The error occurs mainly because the range of the 2nd for loop (shown in bold) cannot be determined at compile time (since it's created in the 1st for loop) , which I perfectly understand and agree, but I can't really figure out any other ways to implement it. So any ideas to get past this 'cause I'm really stuck at the moment!

	elsif rising_edge(clk) then
		nParents <= 2*(pop_sz-elite);
		if valid='1'then
			-- 1st clock cycle
			for i in elite-1 downto 0 loop 
				if fit>best_fit(i) then 
					[b]cnt<=elite -i;[/b]
				end if;
				if i=0 then 
					cont <= '1';
				else 
					cont <= '0';
				end if;
			end loop;
			
			-- 2nd clock cycle
			if ((cnt/=1) and (cnt/=elite) and (cnt/=0)) and cont='1'  and cont2='0' then 
				[b]for j in 0 to cnt-2 loop[/b]
					best_fit(elite-1-j) <= best_fit(elite-1-j-1); 
					elite_indexs(elite-1-j) <= elite_indexs(elite-1-j-1);
					if j=cnt-2 then
						best_fit(elite-cnt) <= fit;
						elite_indexs(elite-cnt) <= index;
						cont2<='1';
					else 
						cont2<='0';
					end if;
				end loop;
					
                        '
                        '
                        '
                        '

			end if;

 

[bansalr]

vhdl loop

For Loop is just to avoid repeating the statement n times. beacuse in synthesis
the hardware is replicated or generated For loop times.

I am not sure whether u can have a fix max value for the range. definately synthesis tool should know that how many time the harwadre has to be replicated.

 

[brightblade]

vhdl for loop synthesis

In order to replicate a cell or a circuit n times I suggest using generate statement instead of for loop. If your intention for using the loop is replicating the cell use generate not for loop...

 

[bpu]

vhdl loop synthesis

for synthesis tool in expression:
for i in x downto y loop
you should use constants x and y.

are you sure, that you expression:
for i in elite-1 downto 0 loop
contain constant elite, or maybe elite is signal? if it is, than is wrong.