The author is not trying to be instructive or at least understandable, as with most IP sources...the micron code is not written straight for newbs like me
-- nand_flash.vhd
-- Jacques Kleynhans 17/01/10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity NAND_FLASH is -- entity declaration
port (
clk : in std_logic; -- Input clock of the system is 40 MHz
mem_clk : inout std_logic; -- Clock generated by the pll1 to be 66.667MHz
rst_low : in std_logic; -- Reset of system is normally low
nand_cad : inout std_logic_vector(15 downto 0); -- CAD: command,address and data before ff
nand_rdy : in std_logic; -- Signal from the memory device, only accesible when high
nand_opr : in std_logic_vector(2 downto 0); -- Select between rd/wr/erase/rd_id/rd_st
nand_ce : out std_logic; --
nand_cle : out std_logic;
nand_tri_en : out std_logic;
nand_ale : out std_logic;
nand_we : out std_logic;
nand_re : out std_logic;
ready : out std_logic
--nand_wp : out std_logic
--nand_lock : out std_logic
);
end entity NAND_FLASH;
architecture ARCH of NAND_FLASH is
------------------- pll1 instantiation -----------------------
component pll1
port(POWERDOWN : in std_logic;
CLKA : in std_logic;
LOCK, GLA : out std_logic);
end component;
---------------------------------------------------------------
type STATE_TYPE is
(idle, rst_1 , rst_2, rst_3, -- reset
rid_1, rid_2, rid_3, rid_4, rid_5, rid_6, rid_7, rid_8, rid_9, -- read id
prog_1, prog_2, prog_3, prog_4, prog_5, prog_6, prog_7, prog_8, prog_9, prog_10, prog_11, prog_12, prog_13, prog_14, prog_15, prog_16, prog_17, prog_18, prog_19, prog_20, prog_21, prog_22, prog_23, prog_24,
read_1, read_2, read_3, read_4, read_5, read_6, read_7, read_8, read_9, read_10, read_11, read_12, read_13, read_14, read_15, read_16, read_17, read_18, read_19, read_20, read_21,
stat_1, stat_2, stat_3, stat_4, stat_5, stat_6 ); --State list program page
signal state_reg, state_next: state_type;
signal nand_cad_reg, nand_cad_next: std_logic_vector(15 downto 0);
signal nand_ce_buf, nand_cle_buf, nand_tri_buf, nand_ale_buf, nand_we_buf, nand_re_buf: std_logic;
signal nand_ce_reg, nand_cle_reg, nand_tri_reg, nand_ale_reg, nand_we_reg, nand_re_reg: std_logic;
signal counter : std_logic_vector(10 downto 0);
begin
------------Port mapping of variables to I/O -----------------
pll1_1 : pll1 port map(POWERDOWN => '1',CLKA => clk, GLA =>mem_clk);
-- setting registers and states to initial conditions
process(mem_clk, rst_low)
begin
if (rst_low = '0') then
state_reg <= idle;
nand_cad_reg <= (others => '0');
nand_ce_reg <= '0'; --always low
nand_cle_reg <= '0';
nand_tri_reg <= '0';
nand_ale_reg <= '1';
nand_we_reg <= '1';
--nand_re_reg <= '0';
elsif (rising_edge(mem_clk)) then
state_reg <= state_next;
nand_cad_reg <= nand_cad_next;
nand_ce_reg <= nand_ce_buf; --always low when working with 2gig flash single die
nand_cle_reg <= nand_cle_buf;
nand_tri_reg <= nand_tri_buf;
nand_ale_reg <= nand_ale_buf;
nand_we_reg <= nand_we_buf;
nand_re_reg <= nand_re_buf;
end if;
end process;
-- next state and functional data path routing
process(state_reg, nand_opr, nand_rdy, nand_cad, nand_cad_reg) --sensitivity list
begin
nand_cad_next <= nand_cad_reg;
counter <= counter;
ready <= '0';
case state_reg is
when idle =>
counter <= (others => '0');
if nand_rdy = '0' then
state_next <= idle;
else
if nand_opr = "000" then --Reset state
state_next <= rst_1;
elsif nand_opr = "001" then --Read ID state
state_next <= rid_1;
elsif nand_opr = "010" then --Read page state
state_next <= read_1;
elsif nand_opr = "011" then --Write Page state
state_next <= prog_1;
elsif nand_opr = "100" then --Erase Block state
state_next <= idle;
elsif nand_opr = "101" then --Read status state
state_next <= stat_1;
elsif nand_opr = "110" then --Reserved state 1
state_next <= idle;
elsif nand_opr = "111" then --Reserved state 2
state_next <= idle;
else -- any other character combinations
state_next <= idle;
end if;
end if;
ready <= '1';
when rst_1 =>
if (nand_rdy = '0') then -- This bit of code will check to see if the memory device is ready to be accessed
state_next <= rst_1;
else
nand_cad_next <= "0000000011111111"; -- 00FFh hex command for reset
state_next <= rst_2;
end if;
when rst_2 =>
state_next <= rst_3;
when rst_3 =>
state_next <= idle;
when rid_1 =>
nand_cad_next <= "0000000010010000"; -- 0090h hex command for read id
state_next <= rid_2;
when rid_2 =>
state_next <= rid_3;
when rid_3 =>
nand_cad_next <= "0000000000000000"; -- 0000h address command for readi id
state_next <= rid_4;
when rid_4 =>
state_next <= rid_5;
when rid_5 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= rid_6;
when rid_6 =>
if unsigned(counter) = 3 then
state_next <= rid_7;
counter <= (others => '0');
else state_next <= rid_5;
end if;
when rid_7 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= rid_8;
when rid_8 =>
if unsigned(counter) = 5 then
state_next <= rid_9;
counter <= (others => '0');
else
nand_cad_next <= nand_cad; -- data is read from the nand_cad port
state_next <= rid_7;
end if;
when rid_9 =>
state_next <= idle;
when prog_1 =>
nand_cad_next <= "0000000010000000"; --80h command used for programming page
state_next <= prog_2;
when prog_2 =>
state_next <= prog_3;
when prog_3 =>
nand_cad_next <= "0000000011111111"; --collomn address 1
state_next <= prog_4;
when prog_4 =>
state_next <= prog_5;
when prog_5 =>
nand_cad_next <= "0000000000000100"; --column address 2
state_next <= prog_6;
when prog_6 =>
state_next <= prog_7;
when prog_7 =>
nand_cad_next <= "0000000011111011"; --row address 1
state_next <= prog_8;
when prog_8 =>
state_next <= prog_9;
when prog_9 =>
nand_cad_next <= "0000000010101010"; --row address 2
state_next <= prog_10;
when prog_10 =>
state_next <= prog_11;
when prog_11 =>
nand_cad_next <= "0000000011000011"; --row address 3
state_next <= prog_12;
when prog_12 =>
state_next <= prog_13;
when prog_13 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= prog_14;
when prog_14 =>
if unsigned(counter) = 2 then
state_next <= prog_15;
counter <= (others => '0');
else state_next <= prog_13;
end if;
when prog_15 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= prog_16; --states are being repeated to create clock for we
when prog_16 =>
if unsigned(counter) = 1057 then
nand_cad_next <= "0000000000010000"; --0010h end command for program page
state_next <= prog_17;
counter <= (others => '0');
else
nand_cad_next <= nand_cad;
state_next <= prog_15;
end if;
when prog_17 =>
state_next <= prog_18;
when prog_18 =>
state_next <= prog_19;
when prog_19 =>
if (nand_rdy = '0') then
state_next <= prog_19;
else
nand_cad_next <= "0000000001110000"; --0070h command for status read
state_next <= prog_20;
end if;
when prog_20 =>
state_next <= prog_21;
when prog_21 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= prog_22;
when prog_22 =>
if unsigned(counter) = 2 then
state_next <= prog_23;
counter <= (others => '0');
else state_next <= prog_21;
end if;
when prog_23 =>
nand_cad_next <= nand_cad; -- data is read from the nand_cad port
state_next <= prog_24;
when prog_24 =>
state_next <= idle;
when read_1 =>
nand_cad_next <= "0000000000000000"; --00h command used for reading a page
state_next <= read_2;
when read_2 =>
state_next <= read_3;
when read_3 =>
nand_cad_next <= "0000000011111111"; --collomn address 1
state_next <= read_4;
when read_4 =>
state_next <= read_5;
when read_5 =>
nand_cad_next <= "0000000000000100"; --column address 2
state_next <= read_6;
when read_6 =>
state_next <= read_7;
when read_7 =>
nand_cad_next <= "0000000011111011"; --row address 1
state_next <= read_8;
when read_8 =>
state_next <= read_9;
when read_9 =>
nand_cad_next <= "0000000010101010"; --row address 2
state_next <= read_10;
when read_10 =>
state_next <= read_11;
when read_11 =>
nand_cad_next <= "0000000011000011"; --row address 3
state_next <= read_12;
when read_12 =>
state_next <= read_13;
when read_13 =>
nand_cad_next <= "0000000000110000"; --0010h end command for program page
state_next <= read_14;
when read_14 =>
state_next <= read_15;
when read_15 =>
state_next <= read_16;
when read_16 =>
if (nand_rdy = '0') then
state_next <= read_16;
else state_next <= read_17;
end if;
when read_17 => -- delay state before data will be read
state_next <= read_18;
when read_18 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= read_19;
when read_19 =>
if unsigned(counter) = 1057 then
state_next <= read_20;
counter <= (others => '0');
else state_next <= read_18;
end if;
when read_20 =>
state_next <= idle;
when read_21 =>
state_next <= idle;
when stat_1 =>
nand_cad_next <= "0000000001110000"; --0070h command for status read
state_next <= stat_2;
when stat_2 =>
state_next <= stat_3;
when stat_3 =>
counter <= std_logic_vector(unsigned (counter) + 1);
state_next <= stat_4;
when stat_4 =>
if unsigned(counter) = 2 then
state_next <= stat_5;
counter <= (others => '0');
else state_next <= stat_3;
end if;
when stat_5 =>
nand_cad_next <= nand_cad; -- data is read from the nand_cad port
state_next <= stat_6;
when stat_6 =>
state_next <= idle;
end case;
end process;
-- look ahead output logic
process(state_next)
begin
-- The initial state set all the control lines to default states
nand_tri_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_cle_buf <= '0';
nand_re_buf <= '1';
case state_next is
when idle =>
when rst_1 =>
when rst_2 =>
nand_tri_buf <= '1';
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
when rst_3 =>
nand_tri_buf <= '1';
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
when rid_1 =>
when rid_2 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when rid_3 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when rid_4 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when rid_5 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when rid_6 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when rid_7 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '0';
when rid_8 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '0';
nand_tri_buf <= '0';
when rid_9 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '0';
when prog_1 =>
when prog_2 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_3 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_4 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_5 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_6 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_7 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_8 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_9 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_10 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_11 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_12 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_13 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_14 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_15 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_16 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_17 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_18 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_19 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_20 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_21 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_22 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when prog_23 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '0';
nand_tri_buf <= '1';
when prog_24 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when stat_1 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when stat_2 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when stat_3 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when stat_4 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when stat_5 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '0';
nand_tri_buf <= '1';
when stat_6 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_1 =>
when read_2 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_3 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_4 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_5 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_6 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_7 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_8 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_9 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_10 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_11 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_12 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_13 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '1';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_14 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_15 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_16 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_17 =>
nand_cle_buf <= '1';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_18 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_19 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
when read_20 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '0';
nand_ale_buf <= '0';
nand_re_buf <= '0';
nand_tri_buf <= '1';
when read_21 =>
nand_cle_buf <= '0';
nand_ce_buf <= '0';
nand_we_buf <= '1';
nand_ale_buf <= '0';
nand_re_buf <= '1';
nand_tri_buf <= '1';
end case;
end process;
-- output signals and port maping
nand_cad <= nand_cad_reg; -- need to ad a delimiting factor eg when tri is low do else Z
nand_tri_en <= nand_tri_reg;
nand_ce <= nand_ce_reg;
nand_cle <= nand_cle_reg;
nand_ale <= nand_ale_reg;
nand_we <= nand_we_reg;
nand_re <= nand_re_reg;
end arch;
W CL207 All reachable assignments to nand_ce_reg assign 0, register removed by optimization nand_flash.vhd (77) NAND_FLASH.srr (38) 08:51:36 Tue Jan 19 compilerReport
W CL190 Optimizing register bit nand_cad(8) to a constant 0 nand_flash.vhd (77) NAND_FLASH.srr (40) 08:51:36 Tue Jan 19 compilerReport
W CL171 Pruning Register bit <3> of nand_cad(7 downto 0) nand_flash.vhd (77) NAND_FLASH.srr 08:51:36 Tue Jan 19 compilerReport
W CL111 All reachable assignments to nand_ce_reg assign '0', register removed by optimization nand_flash.vhd (77) NAND_FLASH.srr (37) 08:51:36 Tue Jan 19 compilerReport
W CD326 Port lock of entity work.pll1 is unconnected nand_flash.vhd (68) NAND_FLASH.srr (24) 08:51:36 Tue Jan 19 compilerReport
W BN269 Library ARC pruning: multiple bidi in cell BIBUF_LVDS. Pruning abandoned. - NAND_FLASH.srr 08:51:36 Tue Jan 19 ProASIC3E Mapper
W BN246 Failed to find top level module 'work.NAND_FLASH' as specified in project file - NAND_FLASH.srr (133) 08:51:36 Tue Jan 19 ProASIC3E Mapper
W CL117 Latch generated from process for signal counter(10 downto 0), probably caused by a missing assignment in an if or case stmt nand_flash.vhd (127) NAND_FLASH.srr (36) 09:51:30 Tue Jan 19 compilerReport
A Feedback mux created for signal nand_re_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area nand_flash.vhd (77) NAND_FLASH.srr (39) 08:51:36 Tue Jan 19 compilerReport
N CL201 Trying to extract state machine for register state_reg nand_flash.vhd (77) NAND_FLASH.srr (56) 08:51:36 Tue Jan 19 compilerReport
N CD232 Using gray code encoding for type state_type nand_flash.vhd (45) NAND_FLASH.srr (23) 08:51:36 Tue Jan 19 compilerReport
N CD720 Setting time resolution to ns std.vhd (123) NAND_FLASH.srr (16) 08:51:36 Tue Jan 19 compilerReport
N CD630 Synthesizing proasic3e.vcc.syn_black_box - NAND_FLASH.srr 08:51:36 Tue Jan 19 compilerReport
N MT322 Clock constraints cover only FF-to-FF paths associated with the clock.. - NAND_FLASH.srr (291) 08:51:36 Tue Jan 19 timingReport
N MT320 This timing report estimates place and route data. Please look at the place and route timing report for final timing.. - NAND_FLASH.srr (289) 08:51:36 Tue Jan 19 timingReport
N MF258 Gated clock conversion disabled - NAND_FLASH.srr (135) 08:51:36 Tue Jan 19 ProASIC3E Mapper
N MF249 Running in 32-bit mode. - NAND_FLASH.srr (134) 08:51:36 Tue Jan 19 ProASIC3E Mapper
N BN225 Writing default property annotation file C:\Actelprj\nand_flash\synthesis\NAND_FLASH.map. - NAND_FLASH.srr (263) 08:51:36 Tue Jan 19 ProASIC3E Mapper
N MF238 Found 11 bit incrementor, 'un4_counter[10]' nand_flash.vhd (221) NAND_FLASH.srr (216) 09:51:30 Tue Jan 19 ProASIC3E Mapper
N MO106 Found ROM, 'ready_1', 64 words by 1 bits nand_flash.vhd NAND_FLASH.srr 09:51:30 Tue Jan 19 ProASIC3E Mapper
W CL117 Latch generated from process for signal counter(10 downto 0), probably caused by a missing assignment in an if or case stmt nand_flash.vhd (127) NAND_FLASH.srr (36) 09:51:30 Tue Jan 19 compilerReport
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