VHDL file IO simulation

[shaiko]

Hello,

I want to write a textio tesbench for this simple VHDL code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
		
entity parity_generator is 
port						
( 		
  CLK : in	std_logic ;
  RST : in std_logic ;
  INPUT : in std_logic_vector ( 1 downto 0 ) ;
  OUTPUT : out std_logic 
) ;	 	 			            
end entity parity_generator ;

architecture synthesizable_parity_generator of parity_generator is	   
begin

process ( CLK , RST ) is 
begin
  if RST = '1' then
    OUTPUT <= 'Z' ;
  elsif rising_edge ( CLK ) then
    OUTPUT <= INPUT ( 0 ) xor INPUT ( 1 ) ;
  end if ;
end process ;

end architecture synthesizable_parity_generator ;

In my TB, I want to feed the above component with a file that looks like this:

00
01
10
11

I want the TB to read a new line from the above file with every clock edge and print the output in a different file.
Please help me write the TB.

 

[TrickyDicky]

What exactly are you having trouble with?

 

[shaiko]

What exactly are you having trouble with?

The syntax...
I want to learn how to use the textio mechanism. Doing so based on my own specific example will help me understand better...

Suppose my stimulus file is named: stimulus.txt and its content is:

00
01
10
11

1.The file is a string...but I need it to be STD_LOGIC_VECTOR. How do I make the conversion?
2.How do I make my test bench read a new line with every new clock ?
3.How do I write back the output to a new file?
4.How do I save the information?

I've found a lot of information regarding textio simulation but couldn't come up with a working TB to learn from.
If you can post a testbench example for the code above it'd be very helpful.

 

[FvM]

Did you review the available textio procedures?

1. Conversion from string to bit_vector is perfomed by the READ() procedure.
2. Perform READLN() and READ() on rising edge.

 

[shaiko]

Did you review the available textio procedures?

Yes. I did. It raised more questions then it answered.
This is why I'm asking someone more knowledgeable then me in the subject to post an example of a TB that does what I described.

 

[TrickyDicky]

We learned by doing, and asking specific questions.
I dont have any code to hand.
Why not just try and we can comment on what you did?

 

[shaiko]

Why not just try and we can comment on what you did?

OK...

This is my basic TB.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
		
entity tb_parity_generator is                                                                            	                                    
end entity tb_parity_generator ;

architecture simulation_tb_parity_generator of parity_generator is

component parity_generator is 
port					
( 		
  CLK : in std_logic ;
  RST : in std_logic ;
  INPUT : in std_logic_vector ( 1 downto 0 ) ;
  OUTPUT : out std_logic 
) ;	 	 				                                       
end component parity_generator ;

signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file 
signal stimulus_output : std_logic ; -- to file

begin

stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
	
simulation : parity_generator 
port map 
( 		
  CLK => stimulus_clk ,
  RST => stimulus_rst ,
  INPUT => stimulus_input ,
  OUTPUT => stimulus_output
) ;	 	 	
             	
end architecture simulation_tb_counter ;

Should I add both IEEE.STD_LOGIC_TEXTIO and STD.TEXTIO ?
What does each one do?

 

[TrickyDicky]

OK...

This is my basic TB.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
		
entity tb_parity_generator is                                                                            	                                    
end entity tb_parity_generator ;

architecture simulation_tb_parity_generator of parity_generator is

component parity_generator is 
port					
( 		
  CLK : in std_logic ;
  RST : in std_logic ;
  INPUT : in std_logic_vector ( 1 downto 0 ) ;
  OUTPUT : out std_logic 
) ;	 	 				                                       
end component parity_generator ;

signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file 
signal stimulus_output : std_logic ; -- to file

begin

stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
	
simulation : parity_generator 
port map 
( 		
  CLK => stimulus_clk ,
  RST => stimulus_rst ,
  INPUT => stimulus_input ,
  OUTPUT => stimulus_output
) ;	 	 	
             	
end architecture simulation_tb_counter ;

Should I add both IEEE.STD_LOGIC_TEXTIO and STD.TEXTIO ?
What does each one do?

std.textio has functions (read/write etc) defined for standard types. It also declares the text file type
ieee.std_logic_textio has functions for std_logic and std_logic_vector types (it is also not a vhdl standard package)

If you use vhdl 2008, all the textio functions are added to the appropriate packages by default (std_logic_1164, numeric_std, fixed_pkg etc) so std_logic_textio is nothing more than a placeholder

 

[shaiko]

So with VHDL 2008 I don't have to add any textio libraries?

 

[TrickyDicky]

you'll still need std.textio if you want to access the text file type, but all the textio is included in the standard libraries.

 

[shaiko]

suppose my input file is named: "input_stimulus.txt" located in:
C:\some_directory\input_stimulus.txt

What files extensions are legal?
Do I have to declare the file? If yes - how?
Do I have to add it to my project? If yes - how?
What are the difference between a TEXT file and other files?

 

[TrickyDicky]

All file extensions are legal. The file extension is meaningless - its just a name. The file must be a text file though.
Yes, you have to declare the file. If you read any textio tutorial or VHDL text book it will tell you:

file my_file : text open read_mode is "c:\some_directory\input_stimulus.txt"; --you can also use linux style formatting inside modelsim

Do you have to add it to your project? no. but remember the path is relative to the directory you're running the simulation in

What are differences between text files and other files?

The text type is declared in textIO as:

type text is file of string;

you can declare new file types if you want. A lot of examples do this:

type int_file_t is file of integer;

so any calls to read(f, x) and write(f, x) require x to be an integer. But how non-text files are formatted is not defined in the VHDL spec and can differ between vendors, so its highly recommended you stick to text files.

 

[shaiko]

All file extensions are legal. The file extension is meaningless - its just a name. The file must be a text file though.

Of topic question,
What if I'm trying to manipulate the contents of a JPEG file in a simulation environment using my HDL?
I have to change its type to text before I do anything? If yes, how is it done?

 

[FvM]

I don't see how processing of unformatted binary files should be specified in VHDL. It's however possible with Verilog system tasks.

For VHDL modelling, I would convert binary files to decimal formatted and vice versa with an external tool.

 

[shaiko]

I don't see how processing of unformatted binary files should be specified in VHDL.

I didn't say it should be part of the VHDL spec. It was a general question...

 

[TrickyDicky]

There are ways you can read binary files in VHDL. In modelsim you can use:

file data_f_t is file of character

and that gives you byte access.

But as a JPEG, that is compressed image data. For raw image data you will need a bitmap.

But I would highly recommend you convert your jpeg to text somehow. it makes file reading easier and more predictable, as well as portable.

 

[FvM]

There are ways you can read binary files in VHDL. In modelsim you can use:

file data_f_t is file of character

and that gives you byte access.

I see that the type definition complies with general VHDL syntax rules. But I didn't expect that Modelsim would support it. Good to know.

 

[TrickyDicky]

I see that the type definition complies with general VHDL syntax rules. But I didn't expect that Modelsim would support it.

Modelsim supports it just fine.
read(f, t) and write(f, t) are supported natively for all file types.

modelsim will return the characters in the order of the file, then from character you can convert to integer easily:

---

Code VHDL - [expand]
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function char_to_slv( c : character ) return std_logic_vector is
begin
    return std_logic_vector(to_unsigned(character'pos(c), 8));
end function char_to_slv;
 
procedure read_bytes( file     f :     data_file_t;
                      variable s : out std_logic_vector ) is
    variable c_buf   : character;
begin
    for i in 0 to (s'length/8) -1 loop
        read(f, c_buf);
 
        s( (8*i) +7 downto i*8 ) := char_to_slv(c_buf);
    end loop;
end procedure read_bytes;

---

I have successfully been reading/writing bitmap files for years using this method.

There was a test done years ago on another forum testing different simulators for binary file IO. IIRC modelsim worked fine. ISIM worked but decided to put some proprietary header ontop of the written binary data and NCSIM just didnt like it.

 

[shaiko]

Back to my TB:

My file (input_stimulus.txt) is written in a text editor and contains the following:

00
01
10
11

The numbers are characters - how do I convert them to std_logic_vectors ?

 

[FvM]

I thought 24h hours would be time enough to try a few lines of textio code.
e.g.

readln(f,l);
read(l,my_slv2);