Hi, guys!
I have a simple code to load a serial input.
Code VHDL - [expand] |
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| ------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
Port
(
Dclk : in STD_LOGIC;
InputL : in STD_LOGIC;
Frame : in STD_LOGIC;
rj_L : out STD_LOGIC_VECTOR (15 downto 0)
);
end test;
architecture Behavioral of test is
signal bit_count : std_logic_vector(4 downto 0) := "10000";
signal input_rdy_flag : std_logic := '0';
signal data_L : std_logic_vector(15 downto 0);
begin
process (Dclk)
begin
if ((Dclk'event) and (Dclk = '0')) then
if (Frame = '1') then
bit_count <= "01111";
input_rdy_flag <= '0';
data_L (conv_integer(bit_count)) <= InputL;
else
bit_count <= bit_count - "00001";
data_L (conv_integer(bit_count)) <= InputL;
if (bit_count = "00000") then
input_rdy_flag <= '1';
end if;
end if;
end if;
if (input_rdy_flag = '1') then
rj_L <= data_L;
end if;
end process;
end Behavioral;
----------------------------------------------------------------------------------- |
And the testbench is
Code VHDL - [expand] |
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| -----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
COMPONENT test
PORT(
Dclk : IN std_logic;
InputL : IN std_logic;
Frame : IN std_logic;
rj_L : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal Dclk : std_logic := '0';
signal InputL : std_logic := '0';
signal Frame : std_logic := '1';
signal rj_L : std_logic_vector(15 downto 0);
constant Dclk_period : time := 10 ns;
constant rj: std_logic_vector(15 downto 0) := x"0020";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
Dclk => Dclk,
InputL => InputL,
Frame => Frame,
rj_L => rj_L
);
-- Clock process definitions
Dclk_process :process
begin
Dclk <= '0';
wait for Dclk_period/2;
Dclk <= '1';
wait for Dclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
InputL <= rj (15);
Frame <= '1';
wait for Dclk_period;
InputL <= rj (14);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (13);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (12);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (11);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (10);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (9);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (8);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (7);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (6);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (5);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (4);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (3);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (2);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (1);
Frame <= '0';
wait for Dclk_period;
InputL <= rj (0);
Frame <= '0';
end process;
END;
-------------------------------------------------------------- |
Could some one tell me why I get fatal error in the process when the clock reach the falling edge in Modelsim.
Please..........................:bang:
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