I don't know, which HDL respectively FPGA textbooks you own, but apparently you missed to read the basic chapter about how hardware logic programming works. It has little to do with sequential programming languages like C, although the syntax seems quite similar, e.g. when looking at iteration constructs. But their meaning can be completely different.I would not be posting on a forum unless I had exhausted all of my other resources, including textbooks.
my_process: process(clk, reset) --only put clock and async reset in here
begin
if reset = '1' then
--async reset for your registers
elsif rising_edge(clk) then --or clk'event and clk = 1 if you are reading an old book or examples
--put your synchronous logic assignments here
end if;
end process;
I don't know, which HDL respectively FPGA textbooks you own, but apparently you missed to read the basic chapter about how hardware logic programming works.
Thanks for the help all.
I'm a little hung up on defining my state machine though. What would make this alot easier is if i can obtain a 'Ready' signal from the asynchronous combinatorial logic block indicating that the calculations have been completed. My first thought is to measure the total gate delay involved in the processing and set a predefined wait period before sending out the ready signal, but this is not exactly what I want to do. Is there a way to signal that the calculations have been completed?
Also, is there any drawback to putting "all" in my sensitivity list rather than just including only the signals needed?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE IEEE.STD_LOGIC_UNSIGNED.all; USE IEEE.numeric_std.all; LIBRARY altera ; USE altera.maxplus2.all; LIBRARY ieee_proposed; --Necessary to convert inputs to fixed point use ieee_proposed.fixed_float_types.all; --add file to project use ieee_proposed.fixed_pkg.all; --add file to project ENTITY LogicBlock3 IS PORT ( R10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); T10 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); R20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); T20 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); R21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); T21 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); R32 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); T32 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Xa : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --Output coordinates Ya : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --Output coordinates END LogicBlock3 ; ARCHITECTURE Behavior OF LogicBlock3 IS SIGNAL T10int : sfixed(T10'high+1 DOWNTO T10'low); SIGNAL T20int : sfixed(T20'high+1 DOWNTO T20'low); SIGNAL T21int : sfixed(T21'high+1 DOWNTO T21'low); SIGNAL T32int : sfixed(T32'high+1 DOWNTO T32'low); SIGNAL D10, D20, D21, D32 : sfixed(7 DOWNTO -3); SIGNAL a1, b1, b2, a2: sfixed(7 DOWNTO -5); SIGNAL c1, c2: sfixed(13 DOWNTO -4); SIGNAL int3a, int4a: sfixed(12 DOWNTO 3); SIGNAL int5: sfixed(14 DOWNTO 0); SIGNAL int6: sfixed(8 DOWNTO -4); SIGNAL Ybint: sfixed(6 DOWNTO 0); CONSTANT Sound : sfixed(1 DOWNTO -4) := "011101"; CONSTANT L : sfixed(7 DOWNTO 0) := "01100000"; CONSTANT W : sfixed(6 DOWNTO 0) := "0101010"; --Accuracy of results depends on number of decimal places retained(-8) --Divide operator cannot exceed 64 bit vector, limits size of above parameters --Parameters may exceed allowed bits(+13) near center of field, yeilds undefined response --Trade off between number of >0 bits and number of <0 bits BEGIN PROCESS (R10, T10, R20, T20, R21, T21, R32, T32, T10int, T20int, T21int, T32int, D10, D20, D21, D32, a1, a2, b1, b2, c1, c2, int3a, int4a, int5, int6, Ybint) BEGIN --Convert input time difference vectors into fixed point vectors T10int <= resize((to_sfixed(signed(unsigned('0' & T10)))), T10int'high, T10int'low); T20int <= resize((to_sfixed(signed(unsigned('0' & T20)))), T20int'high, T20int'low); T21int <= resize((to_sfixed(signed(unsigned('0' & T21)))), T21int'high, T21int'low); T32int <= resize((to_sfixed(signed(unsigned('0' & T32)))), T32int'high, T32int'low); --Determine if T10 is positive or negative D10 <= resize((0 + T10int)/Sound, D10'high, D10'low); IF R10 = "10" THEN D10 <= resize((0 - T10int)/Sound, D10'high, D10'low); END IF; --Determine if T20 is positive or negative D20 <= resize((0 + T20int)/Sound, D20'high, D20'low); IF R20 = "10" THEN D20 <= resize((0 - T20int)/Sound, D20'high, D20'low); END IF; --Determine if T21 is positive or negative D21 <= resize((0 + T21int)/Sound, D21'high, D21'low); IF R21 = "10" THEN D21 <= resize((0 - T21int)/Sound, D21'high, D21'low); END IF; --Determine if T32 is positive or negative D32 <= resize((0 + T32int)/Sound, D32'high, D32'low); IF R32 = "10" THEN D32 <= resize((0 - T32int)/Sound, D32'high, D32'low); END IF; --Calculate variables for input into variable solutions --Solutions based on set of linear equations: --Xa1 + Yb1 + c1 = 0 --Xa2 + Ya2 + c2 = 0 --Solutions: --Y = ((a1 * c2) - (a2 * c1)) / ((a2 * b1) - (a1 * b2)) --X = ((-b2 / a2) * Y) - (c2 / a2) a1 <= resize((-2) * (L / d10), a1'high, a1'low); b1 <= resize((2) * (W / d20), b1'high, b1'low); --Intermediate signals used to avoid trouble caused by exponent operator c1 <= resize(d21 - (b1*(w/2)) + (a1*(l/(-2))), c1'high, c1'low); a2 <= resize(((2) * (L / d21)) + ((0 + 2) * (L / d32)), a2'high, a2'low); b2 <= resize((-2) * (W / d21), b2'high, b2'low);; int3a<= resize(L*(L/d32), int3a'high, int3a'low); int4a<= resize((W+L)*((W-L)/d21), int4a'high, int4a'low); c2 <= resize(d32 + d21 - (int3a) + (int4a), c2'high, c2'low); --Plug above parameters to obtain variable (X,Y) solutions --Intermediate signals required to remain within divide vector limit int5 <=resize(((a1 * c2) - (a2 * c1)), int5'high, int5'low); int6 <=resize(((a2 * b1) - (a1 * b2)), int6'high, int6'low); Ybint <= resize((int5 / int6), Ybint'high, Ybint'low); Ya <= to_stdlogicvector(Ybint); Xa <= to_stdlogicvector(resize((((-b2 / a2) * Ybint)-(c2 / a2)), Xa'high, Xa'low)); END PROCESS ; END Behavior ;
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