This cant be the whole code, as this just shows a reset.
Your assertion is partially correct, but it will only trigger on the edges specified in the eventControl statement ( the @ ).
This cant be the whole code, as this just shows a reset.
Your assertion is partially correct, but it will only trigger on the edges specified in the eventControl statement ( the @ ).
I would prefer to see the original Verilog code to check, if it's synthesizable at all. Otherwise, it would be pointless to convert it to VHDL.
Take care that there can be only one truely edge sensitive condition in the always block. It's clear so far that pon_rst is an asynchronous (level sensitive) condition, but because you didn't show the other code, the nature of rst_hold is unclear.
Error (10818): Can't infer register for "ifc" at test4.vhd(12) because it does not hold its value outside the clock edge.
Take care that there can be only one truely edge sensitive condition in the always block. It's clear so far that pon_rst is an asynchronous (level sensitive) condition
I know that only one truely edge sensitive condition can be implemented in an always block/process, but why ? One can have multiple clocks.. how do you manage a code which needs to handle multiple clocks?
I know that only one truely edge sensitive condition can be implemented in an always block/process, but why ? One can have multiple clocks.. how do you manage a code which needs to handle multiple clocks?
This is just a limitation of FPGA hardware - Registers only have a single clock input. In Asic, multiple clocks per register may be possible if you're using technology that supports it.
In a design with multiple clock domains, no registers ever need multiple clocks.
process(ifc_clk, pon_rst_n, rst_hold_f)beginif(pon_rst_n = '0')then
x1 <= '0';
x2 <= '0';
x3 <= '0';
x4 <= '0';
x5 <= '0';
x6 <= '0';
x7 <= '0';
x8 <= '0';-- you didn't specify the rst_hold_f in the above code, so I'm not including it here-- basically you didn't ask a good questionelsif rising_edge(ifc_clk)then-- synchronous codeendif;endprocess;
This is just a limitation of FPGA hardware - Registers only have a single clock input. In Asic, multiple clocks per register may be possible if you're using technology that supports it.
In a design with multiple clock domains, no registers ever need multiple clocks.
There's no commonly agreed syntax to model a register with multiple clocks in Verilog. In the usual Verilog register modeling template, there can be only one final else statement which "specifies the synchronous logic part of the design" (IEEE 1364.1-2002).
Although 1364.1 isn't part of the recent IEEE 1800 System Verilog standard, it hasn't been replaced by a new RTL synthesis specification. Please correct me, if you know a commonly agreed Verilog Syntax for registers with multiple clocks.
In more practical regard, I understand that the thread is about FPGA synthesis, so registers with multiple clocks aren't an option.