player80
Full Member level 2
If you insist on using variables you will come up a lot of resistance - Using them is seen as "bad form" and make people think of you as a converted software programmer, not someone who thinks in circuits.
well unfortunately that's what I am and I don't think that I'll become a good FPGA circuit designer that quickly.
I'm trying to study that area and pick up information.
The books just said that signals are only required to interconnect processes, while variables are used for local processes (they didn't mention anything about that those are not preferred). Anyway I picked it up thanks.
But it still doesn't solve my original problem.
delay:=delay(3 downto 0) & rdempty_sig;
if ldma_rdy = '1' and delay="00000" and poscnt<1024 then
Adding delay to the empty flag will just make things worse.
original empty flag to read relationship.
I still don't get it, because closer to the end of the buffer "delay" would be 00001 -- meaning it would not read anything from the dcfifo, it continues... 00010 ... still not reading (still delaying) 00100 again .. it would delay the whole read quite a few cycles until 1 disappears in the std_logic_vector until enough data is stacked up in the fifo.
Since the output (12 MHz) is running faster than the input (5 MHz) this should not be a problem?
However it doesn't work as mentioned so there is a problem and indeed I don't understand the circuit...