player80
Full Member level 2
Hi,
I would like to use a dual clock fifo (Altera Quartus II) for transferring data from one clock domain to another one.
Now the problem is that I'm getting duplicate data on the read side from time to time
The input clock has around 5 MHz, the output clock has 12 MHz, the bus is 8bit wide on the input and output.
Can anyone give me some hint where to look for in order to solve that problem?
Read code:
write code:
I would like to use a dual clock fifo (Altera Quartus II) for transferring data from one clock domain to another one.
Now the problem is that I'm getting duplicate data on the read side from time to time
The input clock has around 5 MHz, the output clock has 12 MHz, the bus is 8bit wide on the input and output.
Can anyone give me some hint where to look for in order to solve that problem?
Code:
002e4840 f4 f5 f6 f6 f7 f8 f9 f9 fa fb fc fc fd fe fe ff |................|
002e4850 00 01 01 02 03 03 04 05 06 06 07 08 09 09 0a 0b |................|
002e4860 0b 0c 0d 0e 0e 0f 10 11 11 12 13 13 14 15 16 16 |................|
002e4870 17 18 18 19 1a 1b 1b 1c 1d 1e 1e 1f 20 20 21 22 |............ !"|
002e4880 23 23 24 25 25 26 27 28 28 29 2a 2b 2b 2c 2d 2d |##$%%&'(()*++,--|
002e4890 2e 2f 30 30 31 32 33 33 34 35 35 36 37 38 38 39 |./00123345567889|
002e48a0 3a 3a 3b 3c 3d 3d 3e 3f 40 40 41 42 42 43 44 45 |::;<==>?@@ABBCDE|
002e48b0 45 46 47 47 48 49 4a 4a 4b 4c 4d 4d 4e 4f 4f 50 |EFGGHIJJKLMMNOOP|
002e48c0 51 52 52 53 54 55 55 56 57 57 58 59 5a 5a 5b 5c |QRRSTUUVWWXYZZ[\|
002e48d0 5c 5d 5e 5f 5f 60 61 62 62 63 64 64 65 66 67 67 |\]^__`abbcddefgg|
002e48e0 68 69 6a 6a 6b 6c 6c 6d 6e 6f 6f 70 71 71 72 73 |hijjkllmnoopqqrs|
002e48f0 74 74 75 76 77 77 78 79 79 7a 7b 7c 7c 7d 7e 7e |ttuvwwxyyz{||}~~|
002e4900 7f 80 81 81 82 83 84 84 85 86 86 87 88 89 89 8a |................|
002e4910 8b 8c 8c 8d 8e 8e 8f 90 90 91 92 93 93 94 95 95 |................|
Read code:
Code:
begin
if rising_edge(clock_out) then
ldma_rdy := dma_rdy;
rdreq_sig <= '0';
valid_out <= '0';
if (ldma_rdy = '0') then
poscnt:=0;
end if;
if (ldma_rdy = '1' and poscnt<1024 and rdempty_sig = '0') then
rdreq_sig <= '1';
valid_out <= '1';
--po<=rdusedw_sig(7 downto 0);
po<=q_sig; --std_logic_vector(to_unsigned(counter, 8));
--po<=std_logic_vector(to_unsigned(counter, 8));
counter:=counter+1;
poscnt:=poscnt+1;
end if;
write code:
Code:
if rising_edge(clk_in) then
wrreq_sig <= '0';
data_sig <= x"00";
if (sync_in = '1') then
enabledata:='1';
bytepos:=0;
end if;
if (valid_in = '1' and enabledata = '1') then
bytebuf(7-bytepos):=dat;
bytepos:=bytepos+1;
if (bytepos = 8) then
wrreq_sig <= '1';
data_sig <= std_logic_vector(to_unsigned(counter, 8));
counter := counter+1;
bytepos:=0;
end if;
end if;