VHDL Counter Process Issue

[jerryt]

I have a counter issue though in my tictactoe project design. I need a counter because the design requirements are to delay 2 seconds after the player makes the first tictactoe move.

My problem is the signal twosecwait gets set to '1' after a key is pressed by the player and then the counter will see a key is pressed by the player (twosecwait = '1') and set the cntr :=0. The next clock cycle however when scanning for a player key press the twosecwait signal will again get set high and in the counter process the twosecwait = '1' will be valid again and the cntr will get set back to 0 again. This puts me into an infinite loop where the counter will continuously be getting set back to 0 over and over again and will never count up to 2000 clock cycles until the twosecwait signal gets set to '0'.

Do you have any ideas on how I can do this? I can't set the twosecwait signal in both processes or I will get an "X" value for the twosecwait signal.

I really appreciate everyone's help...Thanks!!

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My counter process:

CNTR_PROC : process(clk)
variable cntr : integer;
begin
if rising_edge(clk) then

cntr_done <= '0'; --cntr_done is a signal declared above that tells us whether the counter if finished or not
if reset = '1' or twosecwait = '1' then --twosecwait is a signal that says a player made his move last clock cycle
cntr := 0;
elsif cntr = 2000 then --this design uses a 1KHz clock so it takes ""2000 clk cycles"" to make a 2 sec wait

cntr_done <= '1';
else
cntr := cntr + 1;
end if;
end if;

end process CNTR_PROC;
---------------------------------------------------

My TicTacToe Algorithm Process (small portion of it):

TTT_ALGORITHM : process(clk)
if rising_edge(clk) then
if reset = 1 then
[RESET SIGNALS]
elsif reset = 0 then
if K1 = '1' then --where square = 10 means the player placed an X in that square
square1 <= "10"; --setting square for player move (making the square a X)
sG1 <= '1';

twosecwait <= '1';
elsif K2 = '1' then --where square = 10 means the player placed an X in that square
square2 <= "10"; --setting square for player move (making the square a X)
sG2 <= '1';
twosecwait <= '1';
end if;
--------------------------------------------------------------

 

[TrickyDicky]

you can separate out the signals in the 2nd process to have their own if trees.
what is the cntr_done signals supposed to do? I dont think you need it.
Also, make the counter a signal rather than a variable so you can read it in the other process.

eg.

--set the twosecwait signal
if cntr = 2000 then
  twosecwait <= '0';

elsif K1 = '1' or K2 = '1' then
  twosecwait <= '1';

end if;

--set the square1 signal
if K1 = '1' then
  square1 <= "10";

elsif K2 = '1' then
  square2 <= "10";

etc

 

[jerryt]

Tricky - thanks for the reply.

My issue is that In the second process I look to see if a key was pressed by the player on the tic-tac-toe board. If the key is pressed I set a flag for the counter which is setting twosecwait = '1'. My design requirements is after a key press is detected we must wait 2 seconds before the machine can make its move on the tic tac toe board.

I use the counter to count 2000 clock cycles (assuming a 1KHz clock is used) to wait the total 2 seconds. The second process setting of twosecwait = '1' is then used by the counter to reset the counter to '0' but then I also need to reset twosecwait = '0' so that upon the next clock cycle I won't be resetting the counter back to 0. This creates an infinite loop of the reseting the counter over and over again since the twosecwait signal will stay equal to '1'.

My algorithm process (not the counter process) will then again look for a key press and reset the twosecwait signal back to '1' and the counter will reset to 0 again. I need to be able to set the twosecwait signal = '1' in the algorithm process and then use this in the counter process for one clock cycle but then set the twosecwait signal back to '0' so that next time through the clock counter process the counter will count and not reset. I also need to make sure that I not do any key scanning in the algorithm process because if I do the twosecwait signal will get reset back to '1' and cause the counter to continuously reset over and over again.

Basically - I have two processes running in my VHDL code program. One process (process 1) sets a signal to a value and the the other process (process 2) uses this same signal to determine what to set other signals. In process 2 I need to however also reset this same signal. This is not allowed in VHDL and will cause the signal to output "X" in simulations. I need to keep the processes separate from each other. How do I get around this issue? Thanks!!

 

[TrickyDicky]

I highly suggest you draw the circuit on a peice of paper (not all at the gate level, but with elements like the counter as a single block with enable and reset inputs). You assume everything is connected to a clock.

This way you will get a better idea of what you want, rather than worrying about the code. What you want to do is very straight forward but I think you are confusing youself with VHDL symmantics. Think about the circuit first, and then write the VHDL/