[SOLVED] [VHDL] Counter + Mux to LED.

[devilish]

Welcome everyone!

I'm beginner in VHDL-coding and I've lack of experience with CPDL-designing. I've project to do... It should work as simple LED-display-tester on the Xilinx XC9500 Device. I've only ISE Webpack to compile and simulate the code in home. But I don't know if it have chance to run into device. Could some one verify the code?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity licznik is
    port ( R : in  STD_LOGIC;
	   CLK : in STD_LOGIC;
	   Z : inout STD_LOGIC_VECTOR (4 downto 0));
end licznik;

architecture a1 of licznik is
begin
	process(CLK)
	begin
		if R='1' then Z<="00000"; 
		elsif rising_edge(CLK) then Z<=Z+1;
		end if; 
	end process;
end a1;		
		
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LED7 is
		port ( Z : in STD_LOGIC_VECTOR (4 downto 0);
		       Q : out STD_LOGIC_VECTOR (15 downto 0));
end LED7;				 
architecture a2 of LED7 is
begin			 
		
		Q<="1111111111111111" when Z="00000" else
			"1111111111111110" when Z="00001" else
			"1111111111111100" when Z="00010" else
			"1111111111111000" when Z="00011" else
			"1111111111110000" when Z="00100" else
			"1111111111100000" when Z="00101" else
			"1111111111000000" when Z="00110" else 
			"1111111110000000" when Z="00111" else
			"1111111100000000" when Z="01000" else 
			"1111111000000000" when Z="01001" else 
			"1111110000000000" when Z="01010" else 
			"1111100000000000" when	Z="01011" else 
			"1111000000000000" when	Z="01100" else 
			"1110000000000000" when	Z="01101" else 
			"1100000000000000" when Z="01110" else 
			"1000000000000000" when Z="01111" else
			"0000000000000000";
				
end a2;
	
library IEEE;
use IEEE.std_logic_1164.all;
	
entity tester is
	port ( RESET : in STD_LOGIC;
			 CLOCK : in STD_LOGIC;
			 WYJSCIE : out STD_LOGIC_VECTOR (15 downto 0));
end tester;

architecture a1 of tester is
	component licznik
		 port ( R : in  STD_LOGIC;
				  CLK : in STD_LOGIC;
			     Z : inout STD_LOGIC_VECTOR (4 downto 0));
	end component;
	
	component LED7
		  port ( Z : in STD_LOGIC_VECTOR (4 downto 0);
				   Q : out STD_LOGIC_VECTOR (15 downto 0));
	end component;
	
signal ZWEW : STD_LOGIC_VECTOR (4 downto 0);
	
begin 

	U1 : licznik port map(CLK=>CLOCK, R=>RESET, Z=>ZWEW);
	U2 : LED7 port map(Z=>ZWEW, Q=>WYJSCIE);

end a1;

In simulation each particular block seems to be ok. But I'm not sure about block with components and port maps.

PS.
I'm sorry for my bad english!

 

[ReComm]

Hi,

1. why you use 5bit counter, you just need 4 bit counter
2. your code will work 1 time as the counter must reach zeros to repeat the LED ON OFF.
3. in order to download to kit , you have to know kit frequency and adjust your code for that in order to be able to see changes on kit

after modification for 4 bit , the leds will be continuously on off

View attachment urcode_MOD_simulation.bmpView attachment urcode_simulation.bmp

Thanks
ReCoMM

 

[TrickyDicky]

this should work forevery. The Z value will wrap when it gets to max. It does not need resetting to zero.

 

[ReComm]

hi TrickyDicky

it will be zero from z = 01111 to 11111 then it will repeat it self again (led will be off longer period than other changes).
and for resource saving in FPGA

Thanks

 

[devilish]

Hi again. Down to logic, my little experience and the simulation clock should work well, but it doesn't. I've been in lab for a while today to test it and result was very, very disappointing. I have made simpler version which is working well. Here's the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity LICZNIK is
    port ( R : in  STD_LOGIC;
	   C : in STD_LOGIC;
	   Z : inout STD_LOGIC_VECTOR (4 downto 0);
		Q : out STD_LOGIC_VECTOR (15 downto 0));
end LICZNIK;

architecture a1 of LICZNIK is
begin
	process(C,R)
		variable cnt : unsigned(4 downto 0);
		begin
			if R='1' then cnt:="00000";
			elsif rising_edge(C) then
				if cnt<15 then
					cnt:=cnt+1;
				else
					cnt:="00000";
				end if;
			end if;
		Z<=std_logic_vector(cnt);
	end process;
	
		with Z select
		Q<="1111111111111111" when "00000",
			"1111111111111110" when "00001",
			"1111111111111100" when "00010",
			"1111111111111000" when "00011",
			"1111111111110000" when "00100",
			"1111111111100000" when "00101",
			"1111111111000000" when "00110",
			"1111111110000000" when "00111",
			"1111111100000000" when "01000", 
			"1111111000000000" when "01001", 
			"1111110000000000" when "01010", 
			"1111100000000000" when	"01011", 
			"1111000000000000" when	"01100", 
			"1110000000000000" when	"01101", 
			"1100000000000000" when "01110", 
			"1000000000000000" when "01111",
			"0000000000000000" when others;
	
	
end a1;

Anyway I think it would be better if it was written in "component-port map" scheme, but it's still "some kind of magic" for me...

 

[TrickyDicky]

make cnt a signal
Connect Z to cnt outside of the process (or just use "with cnt select" instead)

this current code will connect Z to the artimetic output of count, rather than the registered version. But you should NOT have code outside of the clock section. You could also move the Z assignemnt above the cnt assignments (this is where the subtleties of variables can affect your output logic. It is suggested you use only signals until you understand what the difference is).

 

[devilish]

make cnt a signal
Connect Z to cnt outside of the process (or just use "with cnt select" instead)

Thanks for advice, I'll do that to improve the code. ;-)

 

[ReComm]

with port map
============

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity licznik is
port ( R : in STD_LOGIC;
CLK : in STD_LOGIC;
Z : inout STD_LOGIC_VECTOR (3 downto 0));
end licznik;

architecture a1 of licznik is
begin
process(CLK)
begin
if R='1' then Z<="0000";
elsif rising_edge(CLK) then Z<=Z+1;

end if;
end process;
end a1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LED7 is
port ( Z : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (15 downto 0));
end LED7;
architecture a2 of LED7 is
begin

Q<="1111111111111111" when Z="0000" else
"1111111111111110" when Z="0001" else
"1111111111111100" when Z="0010" else
"1111111111111000" when Z="0011" else
"1111111111110000" when Z="0100" else
"1111111111100000" when Z="0101" else
"1111111111000000" when Z="0110" else
"1111111110000000" when Z="0111" else
"1111111100000000" when Z="1000" else
"1111111000000000" when Z="1001" else
"1111110000000000" when Z="1010" else
"1111100000000000" when Z="1011" else
"1111000000000000" when Z="1100" else
"1110000000000000" when Z="1101" else
"1100000000000000" when Z="1110" else
"1000000000000000" when Z="1111" else
"0000000000000000";

end a2;

library IEEE;
use IEEE.std_logic_1164.all;

entity tester is
port ( RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
WYJSCIE : out STD_LOGIC_VECTOR (15 downto 0));
end tester;

architecture a1 of tester is
component licznik
port ( R : in STD_LOGIC;
CLK : in STD_LOGIC;
Z : inout STD_LOGIC_VECTOR (3 downto 0));
end component;

component LED7
port ( Z : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (15 downto 0));
end component;

signal ZWEW : STD_LOGIC_VECTOR (3 downto 0);

begin

U1 : licznik port map(CLK=>CLOCK, R=>RESET, Z=>ZWEW);
U2 : LED7 port map(Z=>ZWEW, Q=>WYJSCIE);

end a1;

I just make small changes and i think it will run

 

[devilish]

Thanks everyone. I've passed my project. When I've been explaining the code, I've told what could I do and how and it went good. Thread SOLVED.