VHDL concatenationns

[ayumolek]

Hye all,
Can I can learn more about concatenations.. I have the problem to combine the output use this operator. Thanks all..

 

[mrflibble]

https://bit.ly/1nzLLgs

 

[TrickyDicky]

Concatenate is as simple as

a <= b & c;

Whats the problem?

 

[shaiko]

post your code please.

 

[ayumolek]

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
entity DECOMPRESS is
port (  
 
decompress0,decompress1,decompress2,decompress3,decompress4,decompress5,decompress6,
decompress7 : buffer std_logic_vector (7 downto 0); 
decompress_full : out std_logic_vector (63 downto 0) --output 64 bit
 
);
    
end DECOMPRESS;
 
architecture Behavioral of DECOMPRESS is
 
signal c_dummy  :std_logic_vector(63 downto 0);
c_dummy <= decompress0&decompress1&decompress2&decompress3&decompress4&decompress5&decompress6&decompress7;

---

 

[shaiko]

You don't "begin" your architecture...You declare signal "c_dummy" and immediately assign to it. Assignment to signals should be done in the architecture body. Then architecture body must be separated from the declaration region with the reserved word "begin".

Also, please note that you assign your concatenated data to "c_dummy" and not to "decompress_full". Don't know if that was your original intention.

If your code still doesn't work, please post ALL of it.
The failure message that your tool asserts may also help...

P.S: Not sure, but I think that the concatenated statement must be inside parentheses (...).

 

[ayumolek]

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
--/RULE/
--architecture NORIDAYU of DECOMPRESS is
--Bit input 64-bit 00100110  11110000  11011010  00000001  11111010  01101100  00000001  00001000
--Output compression 33-bit is 00  11110000  11011010  11  01  10  11 00001000
--From the output to guide/mention (asume that) Bit_0 set to read 2-bit and Bit_1 set to read 8-bit / 01100001
--That is easy to mention system read by 1-bit or 8-bit when process DECOMPRESSION back to original data. 
--So the output 41-bit (33-bit+8-bit) compression is 00  11110000  11011010  11  01  10  11 00001000 / 01100001 
--/Bit0=2-bit and Bit1=8-bit = 01100001/
 
-----------------------libraries to be used are specified here------------------
 
library ieee;
use ieee.std_logic_1164.all; 
 
-----------------------entity declaration with port definitions-----------------
 
entity DECOMPRESS is
port (  
         clk  : in std_logic;
           b    : out std_logic_vector (7 downto 0); --input the end of bitin 
            a  : out std_logic_vector (1 downto 0); --input bit
        bitin   : in std_logic_vector (41 downto 0); --input bit
      decode : in std_logic_vector (7 downto 0);  --input bit
decompress0,decompress1,decompress2,decompress3,decompress4,decompress5,decompress6,decompress7 : buffer std_logic_vector (7 downto 0); 
decompress_full : out std_logic_vector (63 downto 0) --output 64 bit
 
);
    
end DECOMPRESS;
 
-------------------------------architecture of entity-----------------------------
 
architecture Behavioral of DECOMPRESS is
 
signal bit_8    :   std_logic_vector(7 downto 0);
signal bit_2    :   std_logic_vector(1 downto 0);
signal c_dummy  :   std_logic_vector(63 downto 0);
--/clk/
BEGIN
 
--  process (clk)
--begin     
--if (rising_edge (clk)) then
--          input1<=0;
--      else
--          input1<=decompress_in;  
--end if;
--end process;
 
process (decode) --bit7
begin
 
        if (decode(7)='1') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
 
process (bitin)
begin
        if (bitin(41 downto 40)="00") then
            decompress7 <= "00100110";
        elsif(bitin(41 downto 40)="01") then
            decompress7 <= "11111010";
        elsif(bitin(41 downto 40)="10") then
            decompress7 <= "01101100";
        elsif(bitin(41 downto 40)="11") then
            decompress7 <= "00000001";
        end if;
end process;    
 
process (decode) --bit6
    begin
        if (decode(6)='1') then  
            b <= bit_8;
        else
            a <= bit_2;
        end if;
end process;    
 
process (bitin)
begin
    if (bitin(39 downto 32)="00")then
        decompress6 <= "00100110";
    elsif(bitin(39 downto 32)="01")then
        decompress6 <= "11111010";
    elsif(bitin(39 downto 32)="10")then
        decompress6 <= "01101100";
    elsif(bitin(39 downto 32)="11")then
        decompress6 <= "00000001";
    elsif(bitin(39 downto 32)="11110000")then
        decompress6 <= "11110000";
    end if;
end process;
 
process (decode) --bit5
    begin
        if (decode(5)='1') then  
            b <= bit_8;
        else
            a <= bit_2;
        end if;
end process;    
 
process (bitin)
begin
    if (bitin(31 downto 24)="00")then
        decompress5 <= "00100110";
    elsif(bitin(31 downto 24)="01")then
        decompress5 <= "11111010";
    elsif(bitin(31 downto 24)="10")then
        decompress5 <= "01101100";
    elsif(bitin(31 downto 24)="11")then
        decompress5 <= "00000001";
    elsif(bitin(31 downto 24)="11011010")then
        decompress5 <= "11011010";
    end if;
end process;
 
process (decode) --bit4
begin   
        if (decode(4)='0') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
process (bitin)
begin
    if (bitin(23 downto 22)="00") then
        decompress4 <= "00100110";
    elsif(bitin(23 downto 22)="01") then
        decompress4 <= "11111010";
    elsif(bitin(23 downto 22)="10") then
        decompress4 <= "01101100";
    elsif(bitin(23 downto 22)="11") then
        decompress4 <= "00000001";
    end if;
end process;
 
process (decode) --bit3
    begin
        if (decode(3)='0') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
 
process (bitin)
begin
    if (bitin(21 downto 20)="00") then
        decompress3 <= "00100110";
    elsif(bitin(21 downto 20)="01") then
        decompress3 <= "11111010";
    elsif(bitin(21 downto 20)="10") then
        decompress3 <= "01101100";
    elsif(bitin(21 downto 20)="11") then
        decompress3 <= "00000001";
    end if;
end process;
 
process (decode) --bit2
    begin
        if (decode(2)='0') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
 
process (bitin)
begin
    if (bitin(19 downto 18)="00") then
        decompress2 <= "00100110";
    elsif(bitin(19 downto 18)="01") then
        decompress2 <= "11111010";
    elsif(bitin(19 downto 18)="10") then
        decompress2 <= "01101100";
    elsif(bitin(19 downto 18)="11") then
        decompress2 <= "00000001";
    end if;
end process;
 
process (decode) --bit1
    begin
        if (decode(1)='0') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
process (bitin)
begin
    if (bitin(17 downto 16)="00") then
        decompress1 <= "00100110";
    elsif(bitin(17 downto 16)="01") then
        decompress1 <= "11111010";
    elsif(bitin(17 downto 16)="10") then
        decompress1 <= "01101100";
    elsif(bitin(17 downto 16)="11") then
        decompress1 <= "00000001";
    end if;
end process;
 
process (decode) --bit0
begin
        if (decode(0)='1') then  
            a <= bit_2;
        else
            b <= bit_8;
        end if;
end process;    
 
process (bitin)
begin
    if (bitin(15 downto 8)="00") then
        decompress0 <= "00100110";
    elsif(bitin(15 downto 8)="01") then
        decompress0 <= "11111010";
    elsif(bitin(15 downto 8)="10") then
        decompress0 <= "01101100";
    elsif(bitin(15 downto 8)="11") then
        decompress0 <= "00000001";
    elsif(bitin(15 downto 8)="00001000") then
        decompress0 <= "00001000";
    end if;
end process;
-----------------------concatenationns-----------------
 
 
c_dummy <= decompress0&decompress1&decompress2&decompress3&decompress4&decompress5&decompress6&decompress7;
 
 
 
 
end Behavioral;

---

so in my coding, can it appear the output after use the concantanate? after compile & run its no error. by I don't know if the coding its absolute function..

 

[TrickyDicky]

I still dont understand the problem. Your code cannot compile as it has lots of syntax errors, because you have are comparing too few bits in several places and for some processes you are creating latches due to incomplete decodes.

the c_dummy signal will not appear in the compiled design - I assume it is some debug signal for simulation?

 

[FvM]

The purpose of c_dummy is mysterious as well as the mising assignment to the entity output signal.

Why not simply write decompress_full of the concatenation's left-hand-side?

The code has however other issues that aren't related to concatenations. You have e.g. a "multiple driver error" for output signals a and b, because they are assigned in multiple processes.

 

[ayumolek]

so what should I do? I target the decompression bitstream input 42-bit data back to the original data which is 64bit .. I create a table or dictionary to refer return get to the original data. my problem how do I read the instructions in each input bitstream to read 2bit or 8bit, here I am trying to do in a and b

 

[TrickyDicky]

Have you got an architectural diagram of your circuit in gates and registers? I think it would help a lot in this case.
This diagram should be written before any VHDL is written.

 

[ayumolek]

I don't have... but I have the flowchart..

 

[TrickyDicky]

A flowchart is more a software concept or higher level. You need an architectural or implementation diagram before you write VHDL. Remember, HDL is Hardware Description Language. If you dont know what the hardware should be, how can you describe it?