Re: vhdl question
You should try to get a more thorough understanding of the VHDL event concept. You can either have a synchronous (clock edge sensitive) or a combinational (state sensitive) process. In addition, an asynchronous condition can be combined with a clocked process, e.g. as a reset.
But you can't have additional events inside a clocked process. I notice, that your chasing the idea of additional events in a process since long. Apparently you didn't yet get through to the basic VHDL concepts behind.
In my view, there's no room for additional events in a clocked process, e.g. a state machine. If you want to detect a change in a particular input condition, you can compare the present signal state with the registered previous state and act according to the compare result.