adamsogood
Member level 1
Hi,
There are two VHDL coding styles to check the event of clock rising edge:
1. if (clk='1' and clk'event)
2. if (risingedge(clk))
Please suggest me which one is better? and why? Thanks a lot.
There are two VHDL coding styles to check the event of clock rising edge:
1. if (clk='1' and clk'event)
2. if (risingedge(clk))
Please suggest me which one is better? and why? Thanks a lot.