Jan 5, 2007 #1 A adamsogood Member level 1 Joined Jun 15, 2006 Messages 33 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,538 Hi, There are two VHDL coding styles to check the event of clock rising edge: 1. if (clk='1' and clk'event) 2. if (risingedge(clk)) Please suggest me which one is better? and why? Thanks a lot.
Hi, There are two VHDL coding styles to check the event of clock rising edge: 1. if (clk='1' and clk'event) 2. if (risingedge(clk)) Please suggest me which one is better? and why? Thanks a lot.
Jan 5, 2007 #2 gliss Advanced Member level 2 Joined Apr 22, 2005 Messages 691 Helped 75 Reputation 150 Reaction score 16 Trophy points 1,298 Activity points 5,892 rising edge vhdl #1 is more common and I believe has been in the VHDL spec longer. #2 is valid VHDL but looks more like Verilog. I would go with #1.
rising edge vhdl #1 is more common and I believe has been in the VHDL spec longer. #2 is valid VHDL but looks more like Verilog. I would go with #1.
Jan 5, 2007 #3 A agent_009 Member level 2 Joined Dec 17, 2006 Messages 47 Helped 10 Reputation 20 Reaction score 3 Trophy points 1,288 Activity points 1,563 vhdl risingedge both are Ok, #2 is defined in the ieee library, #1 is default vhdl
Jan 6, 2007 #4 rakesh_aadhimoolam Full Member level 4 Joined Mar 14, 2006 Messages 206 Helped 19 Reputation 38 Reaction score 2 Trophy points 1,298 Activity points 2,751 rising edge syntax vhdl Yes..........there is no problem of using both the constructs............. good luck
rising edge syntax vhdl Yes..........there is no problem of using both the constructs............. good luck
Jan 6, 2007 #5 V vinod_g Member level 4 Joined Nov 29, 2006 Messages 71 Helped 8 Reputation 16 Reaction score 2 Trophy points 1,288 Activity points 1,681 vhdl + rising edge 1: In this the statement below will execute when there is event on the clk and the clock =1 means the clock previous value may be O,Z,X among these values 2:but in this it will only from 0 to 1 transition not from Z,X So, according to the need u can use, If any changes , inform ............... Thanks ok
vhdl + rising edge 1: In this the statement below will execute when there is event on the clk and the clock =1 means the clock previous value may be O,Z,X among these values 2:but in this it will only from 0 to 1 transition not from Z,X So, according to the need u can use, If any changes , inform ............... Thanks ok
Jan 30, 2007 #6 dragonight_x Member level 4 Joined Mar 25, 2006 Messages 71 Helped 2 Reputation 4 Reaction score 0 Trophy points 1,286 Location Egypt - Cairo Activity points 1,667 vhdl risingedge Both coding styles are correct ...............you can use either one