Timing constraints for top level I/O come from the I/O characteristics of the other devices on the board that drive those inputs or receive those outputs.
For example, if the input pins of your design are driven by another device that specifies a 4 ns clock to output delay and received by a device that requires 6 ns of setup time, then you would add those constraints as a 4 ns input delay and a 6 ns output delay to the appropriate I/O. This is kind of the most basic type of thing you will deal with for I/O timing constraints. Next up would be some or all of the following:
- Once you notice that the '4ns' or '6 ns' is larger than your desired clock period, but you also know that data only comes in only once every 4th clock cycle, then you'll be getting into adding timing constraints for those I/O that say the signal path is multi-cycle.
- That other part that drives one of your input pins is 6 inches away from your part and your part is the clock source. You'll want to add in ~1 ns delay for the clock and another ~1 ns delay for the input signal to propagate back to your input pins.
- Those I/O pins are actually on a highly loaded capacitive bus which will slow signals down a bit. You may need to account for that as well.
- Maybe there is no real clock input, the I/O are asynchronous. Typically what I will do here is specify them as multi-cycle so there are no warnings about unconstrained I/O.
Kevin Jennings