I have a particularly weird control unit to implement, which generates some control signals based
only on the value of an internal counter, obviously counting clock cycles. Firstly I would like to ask how (un)common is to generate control signals based solely on the number of clock cycle?
Secondly, in order to design this, I've came up with a
process having in its sensitivity list only the counter output signal.
At this point I should note that there is a specific procedure taking place on regular intervals - every 47 clock cycles - (re-reading from the same memory addresses) something that it could be efficiently represented in a programming language with a for-loop.
So, inside that process I've started writing a HUGE sequence of
if...elsif... statements, something I find quite stupid. Is there a better way to implement this (fewer lines of code, most efficient in terms of maintenance, etc)?
Here you can find that procedure which should be done every 47 cycles:
Code VHDL - [expand] |
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| -- One strip has been completely checked. Reset memory counter.
-- Start reading submemory 1. Writing only 16 pixels on submemory 3.
elsif (count = x"050") then -- Cycle number 80
cs_en_col_load <= '1';
cs_colcnt <= "00000";
cs_en_wr_mem3 <= '1';
cs_datasel <= "11";
elsif (count = x"051") then -- Cycle number 81
cs_en_col_load <= '0';
cs_en_wr_mem3 <= '0';
-- Start reading submemory 2. Writing only 16 pixels on submemory 1.
elsif (count = x"60") then -- Cycle number 96
cs_en_wr_mem1 <= '1';
cs_datasel <= "01";
elsif (count = x"61") then -- Cycle number 97
cs_en_wr_mem1 <= '0';
-- Start reading submemory 3. Writing only 16 pixels on submemory 2.
elsif (count = x"70") then -- Cycle number 112
cs_en_wr_mem2 <= '1';
cs_datasel <= "10";
elsif (count = x"71") then -- Cycle number 113
cs_en_wr_mem2 <= '0'; |
Before that, there are some necessary initialization signals, during the first cycles.
Thank you in advance for your time.