i'm a newbie and I need some vhdl code help could you guys please help me with the code of a left and right shift register circuit ith left shift right sift and parallel load capacity? the hint is to use a control input s=1 if shift direction is right or s=0 if direction is left.
signal d: std_logic_vector (7 downto 0);
process(clk,load)
begin
if load='1' then
d<=input;
elsif clk='1' and clk'event then
if s='1' then
d(6 downto 0)<=d(7 downto 1);
d(7)<=din;
else
d(7 downto 1)<=d(6 downto 0);
d(0)<=din;
end if;
end if;
end process;
I just scribbled this out, I haven't checked it thoroughly. That's left as an exercise for the student...