VHDL code help needed!!!!

[mahi.]

i made this code its an alu doing add, addition with carry, subtraction, AND, OR & NOT. its in multiplexer that when certain code enters, it select corresponding operation. but when i compile, it give alot of errors so if u can help me fix these errors tht would be great.



library ieee;

use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mux is
port (a:in std_logic;
b:in std_logic;
cin:in std_logic;
sel:in std_logic;
resut std_logic);
end mux;

architecture structure of mux is
component adding
port(A,B : in std_logic;
Sum,Cout : out std_logic);
end component;
component sub
port ( A, B: in std_logic;
sum,cout: out std_logic);
end component;
component full
Port ( x,y,cin : in bit;
sum, carry ut bit);
end component;
component andgate
port (a,b : in std_logic ;
c : out std_logic);
end component;
component notgate
port (A: in std_logic;
O : out std_logic);
end component;
component or_gate
port (a,b : in std_logic ;
c : out std_logic);
end component;


begin
process(a,b,sel)
begin
case sel is
when "000" =>
Sum<= a xor b;
res<= a and b;

when "001" =>
signal compl:std_logic;
compl <= NOT b;
sum<= a XOR compl;
res<= a AND compl;

when "010" =>
signal s1,s2, s3 : std_logic;
U1:half port map (x,y,s1,s2);
U2:half port map (s1,cin,sum,s3);
Carry <= s2 or s3;

when "011" =>
res <= a and b;

when "100" =>
res <= not A;

when "101" =>
res <= a or b;

when others =>
res := "XXXXXXXX";

end case;
end process;
end mux;

 

[farhada]

Ok, your design has SO MANY errors that is hard to start.

First of all, you go over the code and see that your signals are defined correctly, the signal SUM is defined as STD_LOGIC, but then it is used in a case statement as std_logic_vector. If you go over the list of errors you have you will be able to fix it, but this code has way too many errors.

Also, you can not put component instantiation inside a case statement. I think you need to first look into some simple VHDL code, then write a simple instantiation of a component, then try to write something like this. Because you seems to know the syntax of VHDL but don't understand the scope of declaration and component instantiation.

VHDL is not C++, and VHDL components are not C++ objects that you can use them and drop them any time you like. VHDL is software implementation of silicon and all resources must be physically available at all time and controlled by different levels of logic that will be accessed in parallel and simultaneously.

 

[sumon_dey]

I have studied your code and found some errors.

you have declared a signal inside a process statement. thats illegal. inside the process statement you should declare variable not signal. and you should declare the variable before the "begin" of the process statement.

 

[vipinlal]

First go through some basic vhdl tuto.
-------------------------------
https://vhdlguru.blogspot.com/