malli.3016
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hii buddies.,
recently i started working with FPGA and VHDL coding. Im using .coe file and initializing Block single port ROM ip-core generator in Xilinx 12.4 and 13.4 Xilinx Fpga prototype tool. Taken Top module code and copied that core gen component and your instance device names, and wrote test bench, and my .coe file consists of address locations of 16., i.e (address: 3 downto 0), and data_read is of 8 bit (7 downto 0).
Im not getting any error in (check syntax nor in behavior check syntax)., but im not able to read more than 2 values in my simulation window for Xilinx ISE simulator.,
can any one goes through my code and help me out.
plz help
recently i started working with FPGA and VHDL coding. Im using .coe file and initializing Block single port ROM ip-core generator in Xilinx 12.4 and 13.4 Xilinx Fpga prototype tool. Taken Top module code and copied that core gen component and your instance device names, and wrote test bench, and my .coe file consists of address locations of 16., i.e (address: 3 downto 0), and data_read is of 8 bit (7 downto 0).
Im not getting any error in (check syntax nor in behavior check syntax)., but im not able to read more than 2 values in my simulation window for Xilinx ISE simulator.,
can any one goes through my code and help me out.
plz help
