vhdl code for cosine
The internal memory blocks of FPGA are generally capable of dual port operation, also with Xilinx Spartan, as far as I know. That means you have one sine ROM, e. g. for one quadrant and can access it at two ports, using different addresses and getting different data output for I and Q. You can use a single phase accumulator that is decoded twice to the ROM addresses, with a 90° offset for the Q part.In some applications, a variable phase shift for the second output may be suitable.