vhdl pwm
There are some points, that have to be considered before writing PWM code (respectively trying to copy some existing code):
- the modulation scheme can be natural, regular symmetrical or regular asymmetrical sampling
- PWM modulation input can be either relative (+/- 1 range) or absolute (requested output voltage). In the latter case, a bus voltage measurement has to be processed in the PWM generation. The method is particular useful for a multi-channel (3-phase or more) PWM.
Generally, a ramp generator (mostly triangular), a comparator and optionally a sampler (for regular schemes) forms the PWM generator.