VHDL is NOT a programming language. It is a hardware description language. Using it like a programming language will cause you all sorts of problems.
As to your questions.
1. All simulators have their pros and cons. None of them specific to NoC, as the design will have nothing to do with simulation performance. The main simulators are Mentor's Questa, Cadence NCSim, Aldec's Active HDL and Xilinx Isim. Questa/modelsim is available with a free limited licence from Altera via it's webpack download. Isim is part of the ISE/Vivado design suite (which you may have to pay for). But you will need to pay for a full version of any of these tools.
There is also the open source GHDL - it is free, but as with all open source tools - dont expect any decent support.
2. VHDL is just a text lanuage - so any text editor will do. Notepad++ is pretty good (and free) for windows and has built in VHDL syntax highliting. For Linux there are plenty of free text editors.
3. They both work just fine. Its nothing to do with VHDL itself - its the tools you decide to use.