VHDL code for memory order buffer

[mousbah125]

hi guys i really need the VHDL code for a memory order buffer!! this is a circular buffer implemented with a head pointer and a tail pointer. it is used to allow out of order execution among memory instructions like load and stores

 

[lostinxlation]

The spec is not clear.
To allow out of order execution, you must have a reservation station, but a reservation station usually comes with CAM strucure to match up the physical tag on the data bus to capture the data. Load cannot pass the store if the address matches, and you need to put those restrictions. There are so many things to consider when you run out of order exec, and the detailed spec isn't clear.
To be honest, Id' think it's easier to make it by yourself instead of looking for the codes since the function of reservation stations really depends on the overall microachitecture of the processor and you won't be able to find the one that exactly fits your need.

 

[mousbah125]

i don't know where to start from. i really need a VHDL code as a starting point. it is a project in the computer architecture course and we really don't have enough time to work on it. here are the spec and description

In this project, you are asked to implement a Memory Ordering Buffer (MOB) in VHDL. The top-level block diagram of the MOB is shown in the Memory Ordering file posted in Moodle. The MOB main components are a Store Buffer and a Load Buffer.
The Store Buffer and the Load buffer can be implemented as circular buffers, each with a head pointer and a tail pointer. Loads and stores are assigned entries in the load and store buffer in program order in the front-end of the superscalar pipeline. They enter the buffers out-of-order when they are dispatched to execution from the reservation stations. They are removed when they are retired in the reorder buffer.
The Store Buffer contains address comparators and logic to check for dependences between loads and stores, and bypass network to forward store data to dependent loads. A dispatched load will be either be stalled, forwarded from the Store Buffer using the bypass network, or it will proceed to read data from the cache.
You should assume that the memory execution bandwidth is one load or store per cycle, i.e., the Store Buffer will process a store or a load dispatched from the reservation stations every cycle. Processing a store involves writing it in the Store buffer. Processing a load involves determining if the load needs to be stalled, forwarded, or allowed to proceed to the cache. In case the load needs to be forwarded, the Store Buffer performs an access cycle to read the data and forward it to the load.

Deliverables:
1. You are to implement the Store Buffer of the MOB described above. Using structural VHDL.
2. “sb.vhd” that contains the design of your Store Buffer. Include all other entities you use in this file in separate VHDL files.
3. A testbench file called “sb_tb.vhd” that tests all possible scenarios of store and load execution.
4. Submit the complete modelsim project file of your design using Moodle. One member per group needs to submit the design in Moodle.

 

[lostinxlation]

Yeah, I can promise you won't be able to find it. There are a few features that are distinctive to your microarchitecture and unless someone came up with the same implementation, it's not available. Make it by yourself. Not super difficult.