library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine_cos is
port (
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
sine : buffer std_logic_vector(7 downto 0);
cos : buffer std_logic_vector(7 downto 0));
end sine_cos;
architecture behave_sine_cos of sine_cos is
signal sine_r, cos_r : std_logic_vector(7 downto 0);
begin -- behave_sine_cos
sine <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3));
cos <= cos_r - (sine(7) & sine(7) & sine(7) & sine(7 downto 3));
registers: process (clk, reset)
begin -- process registers
if reset = '0' then -- asynchronous reset (active low)
sine_r <= "00000000";
cos_r <= "01111000";
elsif clk'event and clk = '1' then -- rising clock edge
if (en = '1') then
sine_r <= sine;
cos_r <= cos;
end if;
end if;
end process registers;
end behave_sine_cos;
-------------------------------------------------------------------------------
-- Testbench
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sine_cos_tb is
end sine_cos_tb;
architecture behave of sine_cos_tb is
component sine_cos
port (
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
sine : buffer std_logic_vector(7 downto 0);
cos : buffer std_logic_vector(7 downto 0));
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal en : std_logic := '1';
signal sine : std_logic_vector(7 downto 0);
signal cos : std_logic_vector(7 downto 0);
begin -- behave
clk <= transport not clk after 5 ns;
u1 : sine_cos
port map (
clk ,
reset ,
en ,
sine ,
cos );
process
begin -- process
wait for 50 ns;
reset <= '1';
wait for 10000 ns;
wait;
end process;
end behave;
+----+ +----+
sine | / | -cos | / |
+--->| | |----->| | |---+
| | / | | / | |
| +----+ +----+ |
| |
+-------------------------+
Sherif Welsen said:Please colleagues, I want to collect every single detail about the Direct Digital Synthesizer (NCO). Please send every information you have.
Thanks inadvance, I remain.
Black Jack said:I have this book "Direct Digital Frequency Synthesizers"
by Venceslav F. Kroupa and advice that you read this.
Sherif Welsen said:Black Jack said:I have this book "Direct Digital Frequency Synthesizers"
by Venceslav F. Kroupa and advice that you read this.
How could I get a copy of that book?
please send me flowchart of your nco code.Renjith said:Hi Sherif,
An NCO design has got just 2 major blocks.
Phase accumulator, LUT Rom( to store the phase angles of sine and cos).
I've attached a NCO design document, this gives a detailed explanation for the blocks i mentioned above.
Hope this helps
Hi,
Here is one example of Qadrature oscillator I build and testted on FPGA.
Its a sine wave oscillator.
I posted this code here some time back also it was in verilog.
Code:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sine_cos is port ( clk : in std_logic; reset : in std_logic; en : in std_logic; sine : buffer std_logic_vector(7 downto 0); cos : buffer std_logic_vector(7 downto 0)); end sine_cos; architecture behave_sine_cos of sine_cos is signal sine_r, cos_r : std_logic_vector(7 downto 0); begin -- behave_sine_cos sine <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3)); cos <= cos_r - (sine(7) & sine(7) & sine(7) & sine(7 downto 3)); registers: process (clk, reset) begin -- process registers if reset = '0' then -- asynchronous reset (active low) sine_r <= "00000000"; cos_r <= "01111000"; elsif clk'event and clk = '1' then -- rising clock edge if (en = '1') then sine_r <= sine; cos_r <= cos; end if; end if; end process registers; end behave_sine_cos; ------------------------------------------------------------------------------- -- Testbench ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity sine_cos_tb is end sine_cos_tb; architecture behave of sine_cos_tb is component sine_cos port ( clk : in std_logic; reset : in std_logic; en : in std_logic; sine : buffer std_logic_vector(7 downto 0); cos : buffer std_logic_vector(7 downto 0)); end component; signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal en : std_logic := '1'; signal sine : std_logic_vector(7 downto 0); signal cos : std_logic_vector(7 downto 0); begin -- behave clk <= transport not clk after 5 ns; u1 : sine_cos port map ( clk , reset , en , sine , cos ); process begin -- process wait for 50 ns; reset <= '1'; wait for 10000 ns; wait; end process; end behave;
Hope this helps
Hi,
Sine and cos waves are generated using Quadrature oscillator.
If you integrate sine wave you get cosine wave You integrate this cosine
wave to generate input sine wave...
This is done using digital filter techniqe here in the VHDL code...
Following figure will explain it well....
Code:+----+ +----+ sine | / | -cos | / | +--->| | |----->| | |---+ | | / | | / | | | +----+ +----+ | | | +-------------------------+
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