vhdl code for flash memory

[shrutireddy]

hi i am mtech student working on a project in DRDO BANGLORE . My project is based on flash memory interfacing with FPGA ....now as part of my project i need to write vhdl code for generating write cycle for flash memory by taking clock,write ,data and address as inputs ....can any one help me ...please

 

[sharath666]

Why don't you try writing the code yourself? You just mentioned the inputs. You know what outputs are needed.Generate them accordingly..Get back to us in case you face any issues..

 

[shrutireddy]

i tried for writing the code but i did not get it ....actually i need to write the code for control signals of falshmemory and the output i need to get is the timing cycle of flashmemory including outputs in read and as well as write ...please can you help me with the code .......... i am new to vhdl i dnt have any subject like vhdl in my B.tech OR M.tech ...SO i am very confused about this ..and how to write this code..

 

[sharath666]

I would advise you to do 2 things here
1. Get a good understanding of what you are trying to accomplish by writing this code i.e. what should the behaviour of the signals be for a write as well as a read.
Assume a simple write and read. Don't complicate matters. Then draw a timing diagram(or a waveform of the signal for a write and a read).
2. Pick up a good book on VHDL coding and try learning the language.
We can help you with errors and problems you face in writing the code. But we cannot help you with the 1st point. You have to do that yourself.

 

[nick123]

Chapter 10, page 147 "Design Recipes for FPGAs" by Dr Peter R. Wilson, may help you.

 

[shrutireddy]

can any one help me with the timing digrams for this code

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Code VHDL - [expand]
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library IEEE
USE IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_std.all;
entity write is
port(clock :in std_logic
wr     : in
adress: in
data-in:in 
data-out:out
cs: out
wr-flash:out
addr-flash:out
reser:in0;
architectute of write is
begin
  process(clock,wr)
  begin
    if reset='1';
      cs='1'
      wr-flash='1';
      addr-flash='1';
    elsif(clock'eventand clock='1')
      if(wr='0' and cs='1')
        cs='0'
      elsif(cs='0' and wr-flash='1')
        data-out=data-in;
        addr-flash=adress;
      elsif(wr-flash='0');
        wr-flash='1'
        cs='1'
      end if;
    end if; 
  end process;

---

 

[sharath666]

Errors in this code:
1.Remove write from sensitivity list and add reset. (Refer the web for clocked processes).
2.wr_flash and cs are outputs. You cannot check for an output to be 1 or 0. You can check only an input.
3.Why is data_out not being assigned under reset?
4.It is architecture and not architectute.

 

[TrickyDicky]

Also - use of - instead of _

Dont people know how to use a compiler nowadays?